H8SSLASH2214 datasheet(18/936 Pages) RENESAS

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Rev.4.00 Sep. 18, 2008 Page xviii of lx

REJ09B0189-0400

Item

Page

Revisions (See Manual for Details)

12.3.2 Operation in

Asynchronous Mode

Figure 12.10

Sample Serial

Reception Data

Flowchart (1)

497

Note added

Yes

<End>

[1]

Initialization

Start reception

[2]

Yes

Read RDRF flag in SSR

[4]

[5]

Clear RE bit in SCR to 0

Read ORER, PER, and

FER flags in SSR

Error processing

(Continued on next page)

[3]

Read receive data in RDR, and

clear RDRF flag in SSR to 0

Yes

PER

∨ FER ∨ ORER = 1

RDRF = 1

All data received?

SCI initialization:

The RxD pin is automatically

designated as the receive data

input pin.

Receive error processing and

break detection:

If a receive error occurs, read the

ORER, PER, and FER flags in

SSR to identify the error. After

performing the appropriate error

processing, ensure that the

ORER, PER, and FER flags are

all cleared to 0. Reception cannot

be resumed if any of these flags

are set to 1. In the case of a

framing error, a break can be

detected by reading the value of

the input port corresponding to

the RxD pin.

SCI status check and receive

data read :

Read SSR and check that RDRF

= 1, then read the receive data in

RDR and clear the RDRF flag to

0. Transition of the RDRF flag

from 0 to 1 can also be identified

by an RXI interrupt.

Serial reception continuation

procedure:

To continue serial reception,

before the stop bit for the current

frame is received, read the

RDRF flag, read RDR, and clear

the RDRF flag to 0. The RDRF

flag is cleared automatically

when DMAC or DTC* is

activated by an RXI interrupt and

the RDR value is read.

Note: * The RDRF flag is cleared automatically by DTC

only when the DTC DISEL bit is 0 and

furthermore the transfer counter is not 0.

Therefore the CPU must clear the RDRF flag

when either DISEL is 1 or when DISEL is 0 and

furthermore the transfer counter is 0.

[1]

[2] [3]

[4]

[5]

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