H8SSLASH2214 datasheet(62/936 Pages) RENESAS

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Section 1 Overview

Rev.4.00 Sep. 18, 2008 Page 2 of 872

REJ09B0189-0400

Table 1.1

Overview

Item

Specification

CPU

• General-register machine

⎯ Sixteen 16-bit general registers (also usable as sixteen 8-bit registers

or eight 32-bit registers)

• High-speed operation suitable for realtime control

⎯ Maximum clock rate 16 MHz

⎯ High-speed arithmetic operations (at 16-MHz operation)

8/16/32-bit register-register add/subtract : 62.5 ns

× 16-bit register-register multiply

: 1250 ns

32 ÷ 16-bit regis

ter-register divide

: 1250 ns

• Instruction set suitable for high-speed operation

⎯ Sixty-five basic instructions

⎯ 8/16/32-bit move/arithmetic and logic instructions

⎯ Unsigned/signed multiply and divide instructions

⎯ Powerful bit-manipulation instructions

• Two CPU operating modes

⎯ Normal mode

: 64-kbyte address space (not available in the

H8S/2214 Group)

⎯ Advanced mode : 16-Mbyte address space

Bus controller

• Address space divided into 8 areas, with bus specifications settable

independently for each area

• Chip select output possible for each area

• Choice of 8-bit or 16-bit access space for each area

• 2-state or 3-state access space can be designated for each area

• Number of program wait states can be set for each area

• Burst ROM directly connectable

• External bus release function

DMA controller

(DMAC)

• Choice of short address mode or full address mode

• Four channels in short address mode

Two channels in full address mode

• Transfer possible in repeat mode, block transfer mode, etc.

• Can be activated by internal interrupt

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