H8SSLASH2214 datasheet(21/936 Pages) RENESAS

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Rev.4.00 Sep. 18, 2008 Page xxi of lx

REJ09B0189-0400

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Page

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12.3.4 Operation in

Clocked

Synchronous Mode

Figure 12.23

Sample Serial

Reception Flowchart

515

Note added

Yes

<End>

[1]

Initialization

Start reception

[2]

Yes

Read RDRF flag in SSR

[4]

[5]

Clear RE bit in SCR to 0

Error processing

(Continued below)

[3]

Read receive data in RDR, and

clear RDRF flag in SSR to 0

Yes

ORER = 1

RDRF = 1

All data received?

Read ORER flag in SSR

[1]

[2] [3]

[4]

[5]

SCI initialization:

The RxD pin is automatically

designated as the receive data

input pin.

Receive error processing:

If a receive error occurs, read the

ORER flag in SSR , and after

performing the appropriate error

processing, clear the ORER flag

to 0. Transfer cannot be resumed

if the ORER flag is set to 1.

SCI status check and receive

data read:

Read SSR and check that the

RDRF flag is set to 1, then read

the receive data in RDR and

clear the RDRF flag to 0.

Transition of the RDRF flag from

0 to 1 can also be identified by

an RXI interrupt.

Serial reception continuation

procedure:

To continue serial reception,

before the MSB (bit 7) of the

current frame is received, finish

reading the RDRF flag, reading

RDR, and clearing the RDRF flag

to 0. The RDRF flag is cleared

automatically when the DMAC or

DTC* is activated by a receive

data full interrupt (RXI) request

and the RDR value is read.

<End>

Error processing

Overrun error processing

[3]

Clear ORER flag in SSR to 0

Note: * The RDRF flag is cleared

automatically by DTC only

when the DTC DISEL bit is 0

and furthermore the transfer

counter is not 0. Therefore

the CPU must clear the

RDRF flag when either

DISEL is 1 or when DISEL is

0 and furthermore the

transfer counter is 0.

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