H8SSLASH2214 datasheet(32/936 Pages) RENESAS

32 / 936 page

Rev.4.00 Sep. 18, 2008 Page xxxii of lx

REJ09B0189-0400

2.8.4

Program Execution State......................................................................................... 61

2.8.5

Bus-Released State ................................................................................................. 61

2.8.6

Power-Down State .................................................................................................. 61

2.9

Basic Timing........................................................................................................................ 62

2.9.1

Overview................................................................................................................. 62

2.9.2

On-Chip Memory (ROM, RAM) ............................................................................ 62

2.9.3

On-Chip Supporting Module Access Timing ......................................................... 64

2.9.4

External Address Space Access Timing ................................................................. 65

2.10

Usage Notes ......................................................................................................................... 65

2.10.1 TAS Instruction....................................................................................................... 65

2.10.2 STM/LDM Instruction Usage ................................................................................. 66

2.10.3 Bit Manipulation Instructions ................................................................................. 66

2.10.4 Access Methods for Registers with Write-Only Bits .............................................. 68

Section 3 MCU Operating Modes .......................................................................71

3.1

Overview.............................................................................................................................. 71

3.1.1

Operating Mode Selection ...................................................................................... 71

3.1.2

3.2

Register Descriptions ...........................................................................................................72

3.2.1

Mode Control Register (MDCR) ............................................................................ 72

3.2.2

System Control Register (SYSCR) ......................................................................... 73

3.3

Operating Mode Descriptions .............................................................................................. 75

3.3.1

Mode 4 .................................................................................................................... 75

3.3.2

Mode 5 .................................................................................................................... 75

3.3.3

Mode 6 .................................................................................................................... 76

3.3.4

Mode 7 .................................................................................................................... 76

3.4

Pin Functions in Each Operating Mode ............................................................................... 77

3.5

Memory Map in Each Operating Mode ............................................................................... 77

Section 4 Exception Handling .............................................................................79

4.1

Overview.............................................................................................................................. 79

4.1.1

Exception Handling Types and Priority.................................................................. 79

4.1.2

Exception Handling Operation................................................................................ 80

4.1.3

Exception Sources and Vector Table ...................................................................... 80

4.2

Reset

................................................................................................................................ 82

4.2.1

Overview................................................................................................................. 82

4.2.2

Reset Types............................................................................................................. 82

4.2.3

Reset Sequence ....................................................................................................... 83

4.2.4

Interrupts after Reset............................................................................................... 85

4.2.5

State of On-Chip Supporting Modules after Reset Release .................................... 85

4.3

Traces ................................................................................................................................ 86

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