H8SSLASH2214 datasheet(347/936 Pages) RENESAS

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Section 9 I/O Ports

Rev.4.00 Sep. 18, 2008 Page 287 of 872

REJ09B0189-0400

(b) Mode 7

Setting a P1DDR bit to 1 makes the corresponding port 1 pin an output port, while clearing the

bit to 0 makes the pin an input port.

(2) Port 1 Data Register (P1DR)

P17DR

R/W

P16DR

R/W

P15DR

R/W

P14DR

R/W

P13DR

R/W

P10DR

R/W

P12DR

R/W

P11DR

R/W

Bit

Initial value :

R/W

P1DR is an 8-bit readable/writable register that stores output data for the port 1 pins (P17 to P10).

P1DR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its

previous state after a manual reset and in software standby mode.

(3) Port 1 Register (PORT1)

P17

—*

P16

—*

P15

—*

P14

—*

P13

—*

P10

—*

P12

—*

P11

—*

Bit

Initial value :

R/W

Note: * Determined by the state of pins P17 to P10.

PORT1 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of

output data for the port 1 pins (P17 to P10) must always be performed on P1DR.

If a port 1 read is performed while P1DDR bits are set to 1, the P1DR values are read. If a port 1

read is performed while P1DDR bits are cleared to 0, the pin states are read.

After a power-on reset and in hardware standby mode, PORT1 contents are determined by the pin

states, as P1DDR and P1DR are initialized. PORT1 retains its previous state after a manual reset

and in software standby mode.

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