H8SSLASH2214 datasheet(358/936 Pages) RENESAS

358 / 936 page

Section 9 I/O Ports

Rev.4.00 Sep. 18, 2008 Page 298 of 872

REJ09B0189-0400

(2) Port 3 Data Register (P3DR)

—

Undefined

—

P36DR

R/W

P35DR

R/W

P34DR

R/W

P33DR

R/W

P30DR

R/W

P32DR

R/W

P31DR

R/W

Bit

Initial value :

R/W

P3DR is an 8-bit readable/writable register that stores output data for the port 3 pins (P36 to P30).

Bit 7 is reserved; this bit cannot be modified and will return an undefined value if read.

P3DR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its

previous state after a manual reset and in software standby mode.

(3) Port 3 Register (PORT3)

—

Undefined

—

P36

—*

P35

—*

P34

—*

P33

—*

P30

—*

P32

—*

P31

—*

Bit

Initial value :

R/W

Note: * Determined by the state of pins P36 to P30.

PORT3 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of

output data for the port 3 pins (P36 to P30) must always be performed on P3DR. Bit 7 is reserved;

this bit cannot be modified and will return an undefined value if read.

If a port 3 read is performed while P3DDR bits are set to 1, the P3DR values are read. If a port 3

read is performed while P3DDR bits are cleared to 0, the pin states are read.

After a power-on reset and in hardware standby mode, PORT3 contents are determined by the pin

states, as P3DDR and P3DR are initialized. PORT3 retains its previous state after a manual reset

and in software standby mode.

H8S/2214 Scheda tecnica(PDF) 358 Page - Renesas Technology Corp

H8S/2214 Scheda tecnica(HTML) 358 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL