H8SSLASH2214 datasheet(399/936 Pages) RENESAS

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Section 9 I/O Ports

Rev.4.00 Sep. 18, 2008 Page 339 of 872

REJ09B0189-0400

(2) Port D Data Register (PDDR)

PD7DR

R/W

PD6DR

R/W

PD5DR

R/W

PD4DR

R/W

PD3DR

R/W

PD0DR

R/W

PD2DR

R/W

PD1DR

R/W

Bit

Initial value :

R/W

PDDR is an 8-bit readable/writable register that stores output data for the port D pins (PD7 to

PD0).

PDDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its

previous state after a manual reset and in software standby mode.

(3) Port D Register (PORTD)

PD7

—*

PD6

—*

PD5

—*

PD4

—*

PD3

—*

PD0

—*

PD2

—*

PD1

—*

Bit

Initial value :

R/W

Note: * Determined by the state of pins PD7 to PD0.

PORTD is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of

output data for the port D pins (PD7 to PD0) must always be performed on PDDR.

If a port D read is performed while PDDDR bits are set to 1, the PDDR values are read. If a port D

read is performed while PDDDR bits are cleared to 0, the pin states are read.

After a power-on reset and in hardware standby mode, PORTD contents are determined by the pin

states, as PDDDR and PDDR are initialized. PORTD retains its previous state after a manual reset

and in software standby mode.

(4) Port D MOS Pull-Up Control Register (PDPCR)

PD7PCR

R/W

PD6PCR

R/W

PD5PCR

R/W

PD4PCR

R/W

PD3PCR

R/W

PD0PCR

R/W

PD2PCR

R/W

PD1PCR

R/W

Bit

Initial value :

R/W

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