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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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H8S/2214 Scheda tecnica(PDF) 463 Page - Renesas Technology Corp |
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H8S/2214 Scheda tecnica(HTML) 463 Page - Renesas Technology Corp |
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463 / 936 page  Section 10 16-Bit Timer Pulse Unit (TPU) Rev.4.00 Sep. 18, 2008 Page 403 of 872 REJ09B0189-0400 (2) Examples of Buffer Operation • When TGR is an output compare register Figure 10.19 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B. As buffer operation has been set, when compare match A occurs the output changes and the value in buffer register TGRC is simultaneously transferred to timer general register TGRA. This operation is repeated each time compare match A occurs. For details of PWM modes, see section 10.4.5, PWM Modes. TCNT value TGR0B H'0000 TGR0C Time TGR0A H'0200 H'0520 TIOCA H'0200 H'0450 H'0520 H'0450 TGR0A H'0450 H'0200 Transfer Figure 10.19 Example of Buffer Operation (1) |
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