H8SSLASH2214 datasheet(706/936 Pages) RENESAS

706 / 936 page

Section 18 Electrical Characteristics

Rev.4.00 Sep. 18, 2008 Page 646 of 872

REJ09B0189-0400

18.4.3

Bus Timing

Table 18.8 lists the bus timing.

Table 18.8

Bus Timing

Condition:

CC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = AVCC, VSS = AVSS = 0 V,

φ = 2 to 16 MHz, T

a = –20°C to +75°C (regular specifications),

a = –40°C to +85°C (wide-range specifications)

Item

Symbol

Min.

Max.

Unit

Test Conditions

Address delay time

—

Address setup time

0.5

× t

cyc – 30

—

Figure 18.7,

Figure 18.8,

Figure 18.10

Address hold time

0.5

× t

cyc – 15

—

CS delay time

CSD

—

Figure 18.7,

Figure 18.8

AS delay time

ASD

—

Figure 18.7,

Figure 18.8,

Figure 18.10

RD delay time 1

RSD1

—

Figure 18.7,

Figure 18.8

RD delay time 2

RSD2

—

Figure 18.7,

Figure 18.8,

Figure 18.10

Read data setup time

RDS

—

Read data hold time

RDH

—

Figure 18.7,

Figure 18.8,

Figure 18.10

Read data access time 2

ACC2

—

1.5

× t

cyc – 65

Figure 18.7

Read data access time 3

ACC3

—

2.0

× t

cyc – 65

Figure 18.7,

Figure 18.10

Read data access time 4

ACC4

—

2.5

× t

cyc – 65

Figure 18.8

Read data access time 5

ACC5

—

3.0

× t

cyc – 65

WR delay time 1

WRD1

—

WR delay time 2

WRD2

—

Figure 18.7,

Figure 18.8

WR pulse width 1

WSW1

1.0

× t

cyc – 30

—

Figure 18.7

WR pulse width 2

WSW2

1.5

× t

cyc – 30

—

Figure 18.8

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