H8SSLASH2214 datasheet(763/936 Pages) RENESAS

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Appendix A Instruction Set

Rev.4.00 Sep. 18, 2008 Page 703 of 872

REJ09B0189-0400

A.4

Number of States Required for Instruction Execution

The tables in this section can be used to calculate the number of states required for instruction

execution by the H8S/2000 CPU. Table A.15 indicates the number of instruction fetch, data

read/write, and other cycles occurring in each instruction. Table A.14 indicates the number of

states required for each cycle, depending on its size. The number of states required for execution

of an instruction can be calculated from these two tables as follows:

Execution states = I

× S

I + J × SJ + K × SK + L × SL + M × SM + N × SN

Examples: Advanced mode, program code and stack located in external memory, on-chip

supporting modules accessed in two states with 8-bit bus width, external devices accessed in three

states with one wait state and 16-bit bus width.

1. BSET #0, @FFFFB3:8

From table A.15:

I = L = 2, J = K = M = N = 0

From table A.14:

I = 4,

L = 2

Number of states required for execution = 2

× 4 + 2 × 2 = 12

2. JSR @@30

From table A.15:

I = J = K = 2, L = M = N = 0

From table A.14:

I = SJ = SK = 4

Number of states required for execution = 2

× 4 + 2 × 4 + 2 × 4 = 24

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