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H8S/2214 Scheda tecnica(PDF) 797 Page - Renesas Technology Corp |
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H8S/2214 Scheda tecnica(HTML) 797 Page - Renesas Technology Corp |
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797 / 936 page ![]() Appendix B Internal I/O Register Rev.4.00 Sep. 18, 2008 Page 737 of 872 REJ09B0189-0400 Appendix B Internal I/O Register B.1 Addresses Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Data Bus Width H'EBC0 to H'EFBF MRA MRB SAR SM1 CHNE SM0 DISEL DM1 — DM0 — MD1 — MD0 — DTS — Sz — DAR CRA CRB DTC 16/32* bit H'FDAC DADR0 H'FDAE DACR — DAOE0 — — — — — — D/A converter 8 bit H'FDB4 SCRX — — — — FLSHE — — — Flash 8 bit H'FDE4 SBYCR SSBY STS2 STS1 STS0 OPE — — — Power-down state 8 bit H'FDE5 SYSCR — — INTM1 INTM0 NMIEG MRESE — RAME MCU 8 bit H'FDE6 SCKCR PSTOP — — — — SCK2 SCK1 SCK0 Clock pulse generator, power-down state 8 bit H'FDE7 MDCR — — — — — MDS2 MDS1 MSD0 MCU, ROM 8 bit H'FDE8 H'FDE9 MSTPCRA MSTPCRB MSTPA7 MSTPB7 MSTPA6 MSTPB6 MSTPA5 MSTPB5 MSTPA4 MSTPB4 MSTPA3 MSTPB3 MSTPA2 MSTPB2 MSTPA1 MSTPB1 MSTPA0 MSTPB0 Power-down state 8 bit H'FDEA MSTPCRC MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 No te: * Located in on-chip RAM. The bus width is 32 bits when the DTC accesses this area as register information, and 16 bits otherwise. |
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