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H8S/2214 Scheda tecnica(PDF) 875 Page - Renesas Technology Corp |
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H8S/2214 Scheda tecnica(HTML) 875 Page - Renesas Technology Corp |
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875 / 936 page ![]() Appendix B Internal I/O Register Rev.4.00 Sep. 18, 2008 Page 815 of 872 REJ09B0189-0400 SMR2—Serial Mode Register 2 H'FF88 SCI2 7 C/ A 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/ E 0 R/W 3 STOP 0 R/W 0 CKS0 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W Bit Initial value R/W : : : Multiprocessor Mode Clock Select 0 1 Multiprocessor function disabled Multiprocessor format selected Parity Mode 0 1 Even parity Odd parity Parity Enable 0 1 Parity bit addition and checking disabled Parity bit addition and checking enabled Character Length 0 1 Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted, and it is not possible to choose between LSB-first or MSB-first mode. 8-bit data 7-bit data* Communication Mode 0 1 Asynchronous mode Clocked synchronous mode Stop Bit Length 0 1 1 stop bit 2 stop bits 0 1 0 1 0 1 φ clock φ/4 clock φ/16 clock φ/64 clock |
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