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H8S/2214 Scheda tecnica(PDF) 905 Page - Renesas Technology Corp |
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H8S/2214 Scheda tecnica(HTML) 905 Page - Renesas Technology Corp |
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905 / 936 page ![]() Appendix C I/O Port Block Diagrams Rev.4.00 Sep. 18, 2008 Page 845 of 872 REJ09B0189-0400 R PA3PCR C QD Reset WPCRA Reset WDRA R C QD PA3 RDRA RODRA RPORA PA3DR Reset WDDRA R C QD PA3DDR Reset WODRA RPCRA R C QD PA3ODR * Output enable signal Open-drain control signal Modes 4 to 6 WDDRA: WDRA: WODRA: WPCRA: RDRA: RPORA: RODRA: RPCRA: Note: * Priority order: Address output > Serial clock input > Serial clock output > DR output Write to PADDR Write to PADR Write to PAODR Write to PAPCR Read PADR Read port A Read PAODR Read PAPCR Legend: Bus controller Address output enable SCI module Serial clock output enable Serial clock input enable Serial clock input Serial clock output Figure C.20 Port A Block Diagram (Pin PA3) |
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