H8SSLASH2214 datasheet(117/936 Pages) RENESAS

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Section 2 CPU

Rev.4.00 Sep. 18, 2008 Page 57 of 872

REJ09B0189-0400

End of bus request

Bus request

Program execution

state

Bus-released state

Sleep mode

Exception-handling state

External interrupt

Software standby mode

MRES = high

RES = high

Manual reset state*1

Power-on reset

state*1

Reset state

Hardware standby mode*2

Notes: 1.

From any state except hardware standby mode, a transition to the power-on reset state occurs whenever

RES goes low. From any state except hardware standby mode and the power-on reset state, a transition

to the manual reset state occurs whenever MRES goes low. A transition can also be made to the reset

state when the watchdog timer overflows.

From any state, a transition to hardware standby mode occurs when STBY goes low.

SLEEP

instruction

with

SSBY = 0

SLEEP

instruction

with

SSBY = 1

Interrupt

request

End of bus

request

Bus

request

Request for

exception

handling

End of

exception

handling

Low Power States

STBY = high, RES = low

Figure 2.16 State Transitions

2.8.2

Reset State

When the

RES input goes low all current processing stops and the CPU enters the power-on reset

state. When the

MRES input goes low, the CPU enters the manual reset state. All interrupts are

disabled in the reset state. Reset exception handling starts when the

RES or MRES signal changes

from low to high.

The reset state can also be entered by a watchdog timer overflow. For details, refer to section 11,

Watchdog Timer (WDT).

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