H8SSLASH2214 datasheet(215/936 Pages) RENESAS

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Section 6 Bus Controller

Rev.4.00 Sep. 18, 2008 Page 155 of 872

REJ09B0189-0400

6.6

Idle Cycle

6.6.1

Operation

When the H8S/2214 Group accesses external space, it can insert a 1-state idle cycle (T

I) between

bus cycles in the following two cases: (1) when read accesses between different areas occur

consecutively, and (2) when a write cycle occurs immediately after a read cycle. By inserting an

idle cycle it is possible, for example, to avoid data collisions between ROM, with a long output

floating time, and high-speed memory, I/O interfaces, and so on.

(1) Consecutive Reads between Different Areas

If consecutive reads between different areas occur while the ICIS1 bit in BCRH is set to 1, an idle

cycle is inserted at the start of the second read cycle.

Figure 6.17 shows an example of the operation in this case. In this example, bus cycle A is a read

cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM,

each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in

cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,

and a data collision is prevented.

Address bus

Bus cycle A

Data bus

Bus cycle B

Bus cycle A

Bus cycle B

Long output

floating time

Data

collision

(a) Idle cycle not inserted

(ICIS1 = 0)

(b) Idle cycle inserted

(Initial value ICIS1 = 1)

Address bus

Data bus

CS (area A)

CS (area B)

CS (area A)

CS (area B)

Figure 6.17 Example of Idle Cycle Operation (1)

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