H8SSLASH2214 datasheet(255/936 Pages) RENESAS

255 / 936 page

Section 7 DMA Controller

Rev.4.00 Sep. 18, 2008 Page 195 of 872

REJ09B0189-0400

Bit 14—Source Address Increment/Decrement (SAID)

Bit 13—Source Address Increment/Decrement Enable (SAIDE): These bits specify whether

source address register MARA is to be incremented, decremented, or left unchanged, when data

transfer is performed.

Bit 14

Bit 13

SAID

SAIDE

Description

MARA is fixed

(Initial value)

MARA is incremented after a data transfer

• When DTSZ = 0, MARA is incremented by 1 after a transfer

• When DTSZ = 1, MARA is incremented by 2 after a transfer

MARA is fixed

MARA is decremented after a data transfer

• When DTSZ = 0, MARA is decremented by 1 after a transfer

• When DTSZ = 1, MARA is decremented by 2 after a transfer

Bit 12—Block Direction (BLKDIR)

Bit 11—Block Enable (BLKE): These bits specify whether normal mode or block transfer mode

is to be used. If block transfer mode is specified, the BLKDIR bit specifies whether the source side

or the destination side is to be the block area.

Bit 12

Bit 11

BLKDIR

BLKE

Description

Transfer in normal mode

(Initial value)

Transfer in block transfer mode, destination side is block area

Transfer in normal mode

Transfer in block transfer mode, source side is block area

For operation in normal mode and block transfer mode, see section 7.5, Operation.

Bits 10 to 7—Reserved: Although these bits are readable/writable, only 0 should be written here.

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