H8SSLASH2224 datasheet(35/1071 Pages) RENESAS

35 / 1071 page

Rev. 5.00 Aug 08, 2006 page xxxv of lxxxvi

Item

Page

Revision (See Manual for Details)

642

Table 16.3 amended

φ = 5 MHz*

φ = 8 MHz*

16.3.4 I

2C Bus Mode

Table 16.3 I

2C Transfer

Rate

Note 3 added

Note: 3. The H8S/2258 Group is out of operation.

16.3.6 I

2C Bus Control

646

Table amended

... (AS it might not be a condition to clear, for details, see

section 16.4.8, Operation Using the DTC)

16.4.1 I

2C Bus Data Format 653

Description amended

... in figure 16.3. The clocked synchronous serial format is a

non-addressing format with no acknowledge bit. ...

16.4.2 Initial Setting

Figure 16.6 Flowchart for IIC

Initialization (Example)

655

Figure 16.6 amended

Set ICMR

16.4.3 Master Transmit

Operation

Figure 16.7 Flowchart for

Master Transmit Mode

(Example)

656

Figure 16.7 amended

Yes

[12] Generate stop condition.

Clear IRIC flag in ICCR

Write BBSY = 0 and

SCP = 0 (ICCR)

Write ACKE = 0 (ICCR)

(Clear ACKB = 0)

End

657

Description amended

[6] ... The master device sequentially sends the transmit

clock and the data written to ICDR using the timing shown in

figure 16.8. The at the 9th ...

[12] ... Clear the IRIC flag to 0. Write 0 to BBSY and SCP ...

Figure 16.8 Example of

Master Transmit Mode

Operation Timing (MLS =

WAIT = 0)

658

Figure 16.8 amended

(Before) R/W

→ (After) R/W

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