H8SSLASH2224 datasheet(52/1071 Pages) RENESAS

52 / 1071 page

Rev. 5.00 Aug 08, 2006 page lii of lxxxvi

8.7.5

Activation Source Acceptance ............................................................................. 278

8.7.6

Internal Interrupt after End of Transfer................................................................ 278

8.7.7

Channel Re-Setting .............................................................................................. 279

Section 9 Data Transfer Controller (DTC)................................................................... 281

9.1

Features............................................................................................................................. 281

9.2

Register Descriptions ........................................................................................................ 282

9.2.1

DTC Mode Register A (MRA) ............................................................................ 283

9.2.2

DTC Mode Register B (MRB)............................................................................. 285

9.2.3

DTC Source Address Register (SAR).................................................................. 285

9.2.4

DTC Destination Address Register (DAR).......................................................... 285

9.2.5

DTC Transfer Count Register A (CRA) .............................................................. 286

9.2.6

DTC Transfer Count Register B (CRB)............................................................... 286

9.2.7

DTC Enable Registers A to G, and I (DTCERA to DTCERG, and DTCERI) .... 286

9.2.8

DTC Vector Register (DTVECR)........................................................................ 288

9.3

Activation Sources ............................................................................................................ 289

9.4

Location of Register Information and DTC Vector Table ................................................ 290

9.5

Operation .......................................................................................................................... 294

9.5.1

Normal Mode....................................................................................................... 295

9.5.2

Repeat Mode........................................................................................................ 295

9.5.3

Block Transfer Mode ........................................................................................... 296

9.5.4

Chain Transfer ..................................................................................................... 298

9.5.5

Interrupts.............................................................................................................. 299

9.5.6

Operation Timing................................................................................................. 299

9.5.7

Number of DTC Execution States........................................................................ 301

9.6

Procedures for Using DTC................................................................................................ 302

9.6.1

Activation by Interrupt......................................................................................... 302

9.6.2

Activation by Software ........................................................................................ 302

9.7

Examples of Use of the DTC ............................................................................................ 303

9.7.1

Normal Mode....................................................................................................... 303

9.7.2

Software Activation ............................................................................................. 303

9.8

Usage Notes ...................................................................................................................... 304

9.8.1

Module Stop Mode Setting .................................................................................. 304

9.8.2

On-Chip RAM ..................................................................................................... 304

9.8.3

DTCE Bit Setting................................................................................................. 304

Section 10 I/O Ports............................................................................................................ 305

10.1 Port 1................................................................................................................................. 309

10.1.1 Port 1 Data Direction Register (P1DDR)............................................................. 309

10.1.2 Port 1 Data Register (P1DR)................................................................................ 310

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