H8SSLASH2224 datasheet(37/1071 Pages) RENESAS

37 / 1071 page

Rev. 5.00 Aug 08, 2006 page xxxvii of lxxxvi

Item

Page

Revision (See Manual for Details)

16.4.6 Slave Transmit

Operation

669 to

671

Section 16.4.6 description replaced

Figure 16.18 Example of

Slave Transmit Mode

Operation Timing (MLS = 0)

671

Figure 16.18 replaced

16.4.8 Operation Using the

DTC

Table 16.5 Flags and

Transfer States

673

Table 16.5 amended

Item

Master Transmit

Mode

Master Receive

Mode

Slave Transmit

Mode

Slave Receive

Mode

Slave address +

W bit

Transmission/

reception

Transmission by

DTC (ICDR write)

Transmission by

CPU (ICDR write)

Reception by CPU

(ICDR read)

Reception by CPU

(ICDR read)

Dummy data

read



Processing by

CPU (ICDR read)



Actual data

transmission/rec

eption

Transmission by

DTC (ICDR write)

Reception by

DTC (ICDR read)

Transmission by

DTC (ICDR write)

Reception by DTC

(ICDR read)

16.6 Usage Notes

676

Description amended

1. ... the start condition, read PORT in each I

2C bus output

pin, and check that SCL and SDA are both low. Even if the

ICE bit is set to 1, it is possible to monitor the pin state by

reading the PORT register so long as the DDR I/O port

issue the instruction ...

2. Either of ...

 Read access to ICDR when ICE = 1 and TRS = 0

(including automatic transfer from ICDRS to ICDRR)

678

Note *2 added to table 16.8

φ = 5 MHz*

φ = 8 MHz*

φ = 16 MHz*

φ = 20 MHz*

Table 16.8 Permissible SCL

Rise Time (tsr) Values

Note 2 added

Notes: 1. Supported only by the H8S/2239 Group.

2. The H8S/2258 Group is out of operation.

679

Note *7 added to table 16.9

φ = 5 MHz*

φ = 8 MHz*

Table 16.9 I

2C Bus Timing

(with Maximum Influence of

tSr/tSf)

680

Note 7 added

Note: 7. The H8S/2258 Group is out of operation.

Figure 16.22 Flowchart and

Timing of Start Condition

Instruction Issuance for

Retransmission

681

Figure 16.22 amended

(Before) [2] Determine whether SCL0 is low

→ (After)

Determine whether SCL is low

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