H8SSLASH2224 datasheet(13/1071 Pages) RENESAS

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Rev. 5.00 Aug 08, 2006 page xiii of lxxxvi

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9.2.7 DTC Enable Registers

A to G, and I

286,

287

Section 9.2.7 description replaced and bit table amended

9.2.7

DTC Enable Registers A to G, and I (DTCERA to DTCERG, and DTCERI)

DTCER is a set of registers to specify the DTC activation interrupt source, and comprised of eight

registers; DTCERA to DTCERG, and DTCERI. The correspondence between interrupt sources

and DTCE bits, and vector numbers generated by the interrupt controller are shown in table 9.2.

For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR for reading and

writing. When multiple activation sources are to be set at one time, only at the initial setting,

writing data is enabled after executing a dummy read on the relevant register with all the interrupt

being masked.

Bit

Bit Name

Initial

Value

R/W

Description

DTCEn7

DTCEn6

DTCEn5

DTCEn4

DTCEn3

DTCEn2

DTCEn1

DTCEn0

R/W

DTC Activation Enable

0: Disables an interrupt for DTC activation.

1: Specifies a relevant interrupt source as a DTC

activation source.

[Clearing conditions]

• When the DISEL bit is 1 and the data transfer

has ended

• When the specified number of transfers have

ended

[Retaining condition]

When the DISEL bit is 0 and the specified number

of transfers have not been completed

Note:

n = A to G, and I

9.2.8 DTC Vector Register

(DTVECR)

288

Bit table amended

Bit

Bit Name

Initial

Value

R/W

Description

7SWDTE

R/W

DTC Software Activation Enable

Enables or disables the DTC software activation.

0: Disables the DTC software activation.

1: Enables the DTC software activation.

[Clearing conditions]

• When the DISEL bit is 0 and the specified

number of transfers have not ended

• When 0 is written to the DISEL bit after a

software-activated data transfer end interrupt

(SWDTEND) request has been sent to the CPU.

[Retaining conditions]

• When the DISEL bit is 1 and data transfer has

ended

• When the specified number of transfers have

ended

• When the software-activated data transfer is in

process

9.4 Location of Register

Information and DTC Vector

Table

Table 9.2 Interrupt Sources,

DTC Vector Addresses, and

Corresponding DTCEs

293

DTCE description of IERxI (RxRDY) and IETxI (TxRDY)

amended

DTCEG6 DTCEG5

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