H8SSLASH2224 datasheet(41/1071 Pages) RENESAS

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Rev. 5.00 Aug 08, 2006 page xli of lxxxvi

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23.2.2 External Clock Input

Table 23.4 External Clock

Input Conditions (Duty

Adjustment Circuit Unused)

(2) (H8S/2238B, H8S/2236B)

Table 23.4 External Clock

Input Conditions (Duty

Adjustment Circuit Unused)

(3) (H8S/2238R, H8S/2236R)

Table 23.4 External Clock

Input Conditions (Duty

Adjustment Circuit Unused)

(4) (H8S/2237 Group,

H8S/2227 Group)

775,

776

Tables 23.4 (2) to (4) added

Table 23.4 External Clock

Input Conditions (Duty

Adjustment Circuit Unused)

(5) (H8S/2239 Group)

777

Note amended

Note: When a duty adjustment circuit is not used, maximum

operating frequency is lowered according to the input

waveform. (Example: tEXL = tEXH = 25 ns, tEXr = tEXf = 5 ns,

clock cycle time = 60 ns, and maximum operating frequency

= 16.6 MHz)

23.2.3 Notes on Switching

External Clock

Figure 23.7 External Clock

Switching Timing (Example)

778

Figure 23.7 amended

200 ns or more

clock

(4)

standby time

External

interrupt

Active (External clock 1)

Active (External clock 2)

Software standby mode

23.7.1 Connecting 32.768-

kHz Crystal Resonator

Figure 23.9 Equivalence

Circuit for 32.768-kHz

Oscillator

780

Figure 23.9 amended

Rs = 14 k

Ω (typ)

23.7.2 Handling Pins when

Subclock Not Required

781

Description amended

... LPWRCR must be set to 1. If the SUBSTP bit is not set to

1, transitions to the power-down modes may not complete

normally.

784,

785

Note *5 added to table 24.1

D/A*

Section 24 Power-Down

Mode

Table 24.1 LSI Internal

States in Each Mode

Note 5 added

Note: 5. The analog output value does not satisfy the

specified D/A absolute accuracy when D/A is halted

(retained). However, the H8S/2258 Group, H8S/2238B, and

H8S/2236B satisfy the specified D/A absolute accuracy.

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