H8SSLASH2224 datasheet(30/1071 Pages) RENESAS

30 / 1071 page

Rev. 5.00 Aug 08, 2006 page xxx of lxxxvi

Item

Page

Revision (See Manual for Details)

14.1.3 Transfer Data (Data

Field Contents)

495

Subheading amended

(4) Locking/Unlocking (Control Bits: Setting (H'3, H'A, H'B),

Cancellation: (H'6))

14.3.3 IEBus Master Control

503

R/W description of CTL 3 to 0 amended

R/W

14.4.2 Slave Receive

Operation

Figure 14.10 Error

Occurrence in the Broadcast

Reception (DEE=1)

533

Figure 14.10 amended

Set the RxE flag and the master unit address in IEMA1 and

IEMA2.

15.3.2 Receive Data

552

Description amended

... watch mode, subactive mode, subsleep mode, or ...

15.3.5 Serial Mode Register

(SMR)

555

• Smart Card Interface Mode (When SMIF in SCMR is 1)

Bit 7 GM and bit 6 BLK description added

Bit

Bit Name

Initial

Value

R/W

Description

R/W

GSM Mode

When this bit is set to 1, the SCI operates in GSM

mode. In GSM mode, the timing of the TEND

setting is advanced by 11.0 etu (Elementary Time

Unit: the time for transfer of 1 bit), and clock output

control mode addition is performed. For details,

refer to section 15.7.8, Clock Output Control.

0: Normal smart card interface mode operation

(initial value)

• The TEND flag is generated 12.5 etu (11.5 etu

in the block transfer mode) after the beginning

of the start bit.

• Clock output on/off control only

1: GSM mode operation in smart card interface

mode

• The TEND flag is generated 11.0 etu after the

beginning of the start bit.

• In addition to clock output on/off control,

high/low fixed control is supported (set using

SCR).

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