H8SSLASH2224 datasheet(11/1071 Pages) RENESAS

11 / 1071 page

Rev. 5.00 Aug 08, 2006 page xi of lxxxvi

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1.3.3 Pin Functions

Table 1.7 Pin Functions of

H8S/2239 Group and

H8S/2238 Group

Pin No.

Type

Symbol

TFP-100B

TFP-100BV

TFP-100G

TFP-100GV

FP-100B

FP-100BV

FP-100A*

FP-100AV*

BP-112*

BP-112V*

TBP-112A*

TBP-112AV*

4 I/O

Function

DMA

controller

(DMAC)*

DREQ1

DREQ0

Input

Request DMAC activation.

(Supported only by the H8S/2239 Group.)

TEND1

TEND0

Output

Indicate that the DMAC has ended

transmitting data.

(Supported only by the H8S/2239 Group.)

DACK1

DACK0

Output

These pins function as single address

transmitting acknowledge of DMAC.

(Supported only by the H8S/2239 Group.)

P47 to P40 in I/O ports

L10, L9, K11, K10, K9, K8, H7, J8

Notes: 1. Supported only by the HD64F2238R.

2. Supported only by the H8S/2239 Group.

3. Supported only by the H8S/2238B and H8S/2236B.

4. Supported only by the HD64F2238R and HD64F2239.

5. Measures should be taken to deal with noise, which can

cause operation errors otherwise.

Table 1.8 Pin Functions of

H8S/2237 Group and

H8S/2227 Group

57 to

Table 1.8 amended

FP-100B*

FP-100BV*

FP-100A*

FP-100BAV*

RES*3 STBY*3 NMI*3

Notes amended

Notes: 1. Supported only by masked ROM version.

2. Supported only by the HD6432227.

3. Measures should be taken to deal with noise, which can

cause operation errors otherwise.

3.4 Memory Map in Each

Operating Mode

Figure 3.7 H8S/2235 and

H8S/2225 Memory Map in

Each Operating Mode

115

Figure 3.7 amended

(Before) On-chip RAM

→ (After) On-chip ROM

5.1 Features

Figure 5.1 Block Diagram of

Interrupt Controller

128

Figure 5.1 amended

(Before) IRQ

→ (After) IRQ

5.3.2 IRQ Enable Register

(IER)

131

Description amended

(Before)

IRQn → (After) IRQn

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