H8SSLASH2224 datasheet(79/1071 Pages) RENESAS

79 / 1071 page

Rev. 5.00 Aug 08, 2006 page lxxix of lxxxvi

Section 5 Interrupt Controller

Table 5.1

Pin Configuration ................................................................................................... 129

Table 5.2

Interrupt Sources, Vector Addresses, and Interrupt Priorities ................................ 137

Table 5.3

Interrupt Control Modes......................................................................................... 142

Table 5.4

Interrupts Selected in Each Interrupt Control Mode (1) ......................................... 143

Table 5.5

Interrupts Selected in Each Interrupt Control Mode (2) ......................................... 144

Table 5.6

Operations and Control Signal Functions in Each Interrupt Control Mode ........... 144

Table 5.7

Interrupt Response Times....................................................................................... 150

Table 5.8

Number of States in Interrupt Handling Routine Execution Status........................ 151

Table 5.9

Interrupt Source Selection and Clear Control......................................................... 153

Section 7 Bus Controller

Table 7.1

Pin Configuration ................................................................................................... 167

Table 7.2

Bus Specifications for Each Area (Basic Bus Interface) ........................................ 177

Table 7.3

Data Buses Used and Valid Strobes ....................................................................... 182

Table 7.4

Pin States in Idle Cycle........................................................................................... 196

Table 7.5

Pin States in Bus Released State............................................................................. 197

Section 8 DMA Controller (DMAC)

Table 8.1

Pin Configuration ................................................................................................... 205

Table 8.2

Short Address Mode and Full Address Mode (Channel 0)..................................... 206

Table 8.3

DMAC Activation Sources..................................................................................... 232

Table 8.4

DMAC Transfer Modes.......................................................................................... 234

Table 8.5

Table 8.6

Table 8.7

Table 8.8

Table 8.9

Table 8.10

Table 8.11

DMAC Channel Priority Order .............................................................................. 271

Table 8.12

Interrupt Sources and Priority Order ...................................................................... 275

Section 9 Data Transfer Controller (DTC)

Table 9.1

Activation Source and DTCER Clearance ............................................................. 289

Table 9.2

Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs ................ 292

Table 9.3

Table 9.4

Table 9.5

Table 9.6

DTC Execution Status ............................................................................................ 301

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