H8SSLASH2224 datasheet(23/1071 Pages) RENESAS

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Rev. 5.00 Aug 08, 2006 page xxiii of lxxxvi

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11.3.4 Timer Interrupt

Enable Register (TIER)

391

Description amended

... for each channel. The TPU of the H8S/2227 Group has a

total of three TIER registers, one each for channels 0 to 2. In

other groups, the TPU has a total of six TIER registers, one

each for channels 0 to 5. Care is required since ...

391,

392

TCIEU, TGIED, TGIEC description amended

... in channels 1, 2, 4*, and 5* ... channels 0 and 3*, ...

392

Note * added

Note: * Not available in the H8S/2227 Group.

11.3.5 Timer Status

393

Description amended

... of each channel. The TPU of the H8S/2227 Group has a

total of three TSR registers, one each for channels 0 to 2. In

other groups, the TPU has a total of six TSR registers, one

each for channels 0 to 5.

393,

394

Table amended

... channels 1, 2, 4*

3, and 5*3 ... channels 0 and 3*3

395

Note 3 added

Note: 3. Not available in the H8S/2227 Group.

11.3.6 Timer Counter

(TCNT)

396

Description amended

... readable/writable counters. The TPU of the H8S/2227

Group has a total of three TCNT registers, one each for

channels 0 to 2. In other groups, the TPU has a total of six

TCNT registers, one each for channels 0 to 5.

11.3.7 Timer General

396

Description amended

... input capture registers. The TPU of the H8S/2227 Group

has a total of four TGR registers, two for channel 0 and one

each for channels 1 and 2. In other groups, the TPU has a

total of eight TGR registers, two each for channels 0 and 3,

and one each for channels 1, 2, 4, and 5.

11.3.8 Timer Start Register

(TSTR)

396

Description amended

In the H8S/2227 Group, TSTR selects operate/stop for

channels 0 to 2. In other groups, TSTR selects operate/stop

for channels 0 to 5. When setting ...

Table amended

CDT5* CDT4* CDT3*

Note * added

Note: * In the H8S/2227 Group, bits 5 to 3 are reserved.

The write value should always be 0.

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