H8SSLASH2224 datasheet(69/1071 Pages) RENESAS

69 / 1071 page

Rev. 5.00 Aug 08, 2006 page lxix of lxxxvi

Figure 8.15 Operation in Block Transfer Mode (BLKDIR = 1) ................................................ 253

Figure 8.16 Operation Flow in Block Transfer Mode ............................................................... 254

Figure 8.17 Example of Block Transfer Mode Setting Procedure............................................. 255

Figure 8.18 Example of DMA Transfer Bus Timing................................................................. 256

Figure 8.19 Example of Short Address Mode Transfer ............................................................. 257

Figure 8.20 Example of Full Address Mode Transfer (Cycle Steal) ......................................... 258

Figure 8.21 Example of Full Address Mode Transfer (Burst Mode)......................................... 259

Figure 8.22 Example of Full Address Mode Transfer (Block Transfer Mode) ......................... 260

Figure 8.23 Example of

DREQ Pin Falling Edge Activated Normal Mode Transfer................ 261

Figure 8.24 Example of

DREQ Pin Falling Edge Activated Block Transfer Mode Transfer.... 262

Figure 8.25 Example of

DREQ Pin Low Level Activated Normal Mode Transfer................... 263

Figure 8.26 Example of

DREQ Pin Low Level Activated Block Transfer Mode Transfer....... 264

Figure 8.27 Example of Single Address Mode Transfer (Byte Read) ....................................... 265

Figure 8.28 Example of Single Address Mode (Word Read) Transfer...................................... 266

Figure 8.29 Example of Single Address Mode Transfer (Byte Write) ...................................... 267

Figure 8.30 Example of Single Address Mode Transfer (Word Write)..................................... 268

Figure 8.31 Example of

DREQ Pin Falling Edge Activated Single Address Mode Transfer.... 269

Figure 8.32 Example of

DREQ Pin Low Level Activated Single Address Mode Transfer....... 270

Figure 8.33 Example of Multi-Channel Transfer....................................................................... 272

Figure 8.34 Example of Procedure for Continuing Transfer on Channel Interrupted by NMI

Interrupt.................................................................................................................. 273

Figure 8.35 Example of Procedure for Forcibly Terminating DMAC Operation...................... 274

Figure 8.36 Example of Procedure for Clearing Full Address Mode ........................................ 274

Figure 8.37 Block Diagram of Transfer End/Transfer Break Interrupt ..................................... 275

Figure 8.38 DMAC Register Update Timing............................................................................. 276

Figure 8.39 Contention between DMAC Register Update and CPU Read................................ 277

Section 9 Data Transfer Controller (DTC)

Figure 9.1

Block Diagram of DTC .......................................................................................... 282

Figure 9.2

Block Diagram of DTC Activation Source Control ............................................... 290

Figure 9.3

The Location of the DTC Register Information in the Address Space................... 291

Figure 9.4

Correspondence between DTC Vector Address and Register Information ............ 291

Figure 9.5

Flowchart of DTC Operation.................................................................................. 294

Figure 9.6

Memory Mapping in Normal Mode ....................................................................... 295

Figure 9.7

Memory Mapping in Repeat Mode ........................................................................ 296

Figure 9.8

Memory Mapping in Block Transfer Mode ........................................................... 297

Figure 9.9

Chain Transfer Operation ....................................................................................... 298

Figure 9.10 DTC Operation Timing (Example in Normal Mode or Repeat Mode) .................. 299

Figure 9.11 DTC Operation Timing (Example of Block Transfer Mode, with Block

Size of 2) ................................................................................................................ 300

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