H8SSLASH2224 datasheet(453/1071 Pages) RENESAS

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Section 11 16-Bit Timer Pulse Unit (TPU)

Rev. 5.00 Aug 08, 2006 page 367 of 982

REJ09B0054-0500

11.3.1

Timer Control Register (TCR)

The TCR registers control the TCNT operation for each channel. The TPU of the H8S/2227 Group

has a total of three TCR registers, one each for channels 0 to 2. In other groups, the TPU has a

total of six TCR registers, one each for channels 0 to 5. TCR register settings should be made only

when TCNT operation is stopped.

Bit

Bit Name

Initial Value

R/W

Description

CCLR2

CCLR1

CCLR0

R/W

Counter Clear 2 to 0

These bits select the TCNT counter clearing source.

See tables 11.3 and 11.4 for details.

CKEG1

CKEG0

R/W

Clock Edge 1 and 0

These bits select the input clock edge. When the

input clock is counted using both edges, the input

clock period is halved (e.g.

φ/4 both edges = φ/2

rising edge). If phase counting mode is used on

channels 1, 2, 4*, and 5*, this setting is ignored and

the phase counting mode setting has priority. Internal

clock edge selection is valid when the input clock is

φ/4 or slower. This setting is ignored if the input clock

φ/1, or when overflow/underflow of another channel

is selected.

00: Count at rising edge

01: Count at falling edge

×: Count at both edges

Legend:

×: Don’t care

TPSC2

TPSC1

TPSC0

R/W

Time Prescaler 2 to 0

These bits select the TCNT counter clock. The clock

source can be selected independently for each

channel. See tables 11.5 to 11.10 for details.

Note:

* Not available in the H8S/2227 Group.

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