H8SSLASH2224 datasheet(458/1071 Pages) RENESAS

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Section 11 16-Bit Timer Pulse Unit (TPU)

Rev. 5.00 Aug 08, 2006 page 372 of 982

REJ09B0054-0500

11.3.2

Timer Mode Register (TMDR)

The TMDR registers are used to set the operating mode for each channel. The TPU of the

H8S/2227 Group has a total of three TMDR registers, one each for channels 0 to 2. In other

groups, the TPU has a total of six TMDR registers, one each for channels 0 to 5. TMDR register

settings should be made only when TCNT operation is stopped.

Bit

Bit Name

Initial Value

R/W

Description

7, 6

—

All 1

—

Reserved

These bits are always read as 1 and cannot be

modified.

BFB

R/W

Buffer Operation B

Specifies whether TGRB is to operate in the normal

way, or TGRB and TGRD are to be used together for

buffer operation. When TGRD is used as a buffer

generated.

In channels 1, 2, 4*, and 5*, which have no TGRD,

bit 5 is reserved. It is always read as 0 and cannot be

modified.

0: TGRB operates normally

1: TGRB and TGRD used together for buffer

operation

BFA

R/W

Buffer Operation A

Specifies whether TGRA is to operate in the normal

way, or TGRA and TGRC are to be used together for

buffer operation. When TGRC is used as a buffer

generated.

In channels 1, 2, 4*, and 5*, which have no TGRC,

bit 4 is reserved. It is always read as 0 and cannot be

modified.

0: TGRA operates normally

1: TGRA and TGRC used together for buffer

operation

MD3

MD2

MD1

MD0

R/W

Modes 3 to 0

These bits are used to set the timer operating mode.

MD3 is a reserved bit. The write value should always

be 0. See table 11.11 for details.

Note:

* Not available in the H8S/2227 Group.

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