H8SSLASH2224 datasheet(480/1071 Pages) RENESAS

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Section 11 16-Bit Timer Pulse Unit (TPU)

Rev. 5.00 Aug 08, 2006 page 394 of 982

REJ09B0054-0500

Bit

Bit Name

Initial value

R/W

Description

3TGFD

R/(W)*

Input Capture/Output Compare Flag D

Status flag that indicates the occurrence of TGRD

input capture or compare match in channels 0 and

In channels 1, 2, 4*

3, and 5*3, bit 3 is reserved. It is

always read as 0 and cannot be modified.

[Setting conditions]

• When TCNT = TGRD while TGRD is functioning

as output compare register

• When TCNT value is transferred to TGRD by

input capture signal while TGRD is functioning

as input capture register

[Clearing conditions]

• When DTC is activated by TGID interrupt while

DISEL bit of MRB in DTC is 0 with the transfer

counter not being 0

• When 0 is written to TGFD after reading TGFD

= 1

2TGFC

R/(W)*

Input Capture/Output Compare Flag C

Status flag that indicates the occurrence of TGRC

input capture or compare match in channels 0 and

In channels 1, 2, 4*

3, and 5*3, bit 2 is reserved. It is

always read as 0 and cannot be modified.

[Setting conditions]

• When TCNT = TGRC while TGRC is functioning

as output compare register

• When TCNT value is transferred to TGRC by

input capture signal while TGRC is functioning

as input capture register

[Clearing conditions]

• When DTC is activated by TGIC interrupt while

DISEL bit of MRB in DTC is 0 with the transfer

counter not being 0

• When 0 is written to TGFC after reading TGFC

= 1

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