Motore di ricerca datesheet componenti elettronici
  Italian  ▼
ALLDATASHEETIT.COM

X  

H8S/2224 Scheda tecnica(PDF) 508 Page - Renesas Technology Corp

Il numero della parte H8S/2224
Spiegazioni elettronici  16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series
PDF  1071 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8S/2224 Scheda tecnica(HTML) 508 Page - Renesas Technology Corp

Back Button H8S/2224 Datasheet HTML 504Page - Renesas Technology Corp H8S/2224 Datasheet HTML 505Page - Renesas Technology Corp H8S/2224 Datasheet HTML 506Page - Renesas Technology Corp H8S/2224 Datasheet HTML 507Page - Renesas Technology Corp H8S/2224 Datasheet HTML 508Page - Renesas Technology Corp H8S/2224 Datasheet HTML 509Page - Renesas Technology Corp H8S/2224 Datasheet HTML 510Page - Renesas Technology Corp H8S/2224 Datasheet HTML 511Page - Renesas Technology Corp H8S/2224 Datasheet HTML 512Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 508 / 1071 page
background image
Section 11 16-Bit Timer Pulse Unit (TPU)
Rev. 5.00 Aug 08, 2006 page 422 of 982
REJ09B0054-0500
Phase Counting Mode Application Example: Figure 11.30 shows an example in which phase
counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo
motor 2-phase encoder pulses in order to detect the position or speed.
Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input
to TCLKA and TCLKB.
Channel 0 operates with TCNT counter clearing by TGRC_0 compare match; TGRA_0 and
TGRC_0 are used for the compare match function, and are set with the speed control cycle and
position control cycle. TGRB_0 is used for input capture, with TGRB_0 and TGRD_0 operating
in buffer mode. The channel 1 counter input clock is designated as the TGRB_0 input capture
source, and detection of the pulse width of 2-phase encoder 4-multiplication pulses is performed.
TGRA_1 and TGRB_1 for channel 1 are designated for input capture, channel 0 TGRA_0 and
TGRC_0 compare matches are selected as the input capture source, and the up/down-counter
values for the control cycles are stored.
This procedure enables accurate position/speed detection to be achieved.
TCNT_1
TCNT_0
Channel 1
TGRA_1
(speed cycle capture)
TGRA_0
(speed control cycle)
TGRB_1
(position cycle capture)
TGRC_0
(position control cycle)
TGRB_0 (pulse width capture)
TGRD_0 (buffer operation)
Channel 0
TCLKA
TCLKB
Edge
detection
circuit
+
-
+
-
Figure 11.30 Phase Counting Mode Application Example



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Scheda tecnica Scarica

Go To PDF Page


Link URL



Lei ha avuto il aiuto da alldatasheet?  [ DONATE ] 

Di alldatasheet   |   Richest di pubblicita   |   contatti   |   Privacy Policy   |   Collegamento alla scheda tecnica    |   scambio Link   |   Ricerca produttore
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com