H8SSLASH2224 datasheet(884/1071 Pages) RENESAS

884 / 1071 page

Section 24 Power-Down Modes

Rev. 5.00 Aug 08, 2006 page 798 of 982

REJ09B0054-0500

24.8

Subsleep Mode

24.8.1

Transition to Subsleep Mode

When the SLEEP instruction is executed with the SSBY bit in SBYCR = 0, the LSON bit in

LPWRCR = 1, and the PSS bit in TCSR_1 (WDT_1) = 1 in subactive mode, CPU operation shifts

to subsleep mode.

In subsleep mode, the CPU is stopped. Peripheral modules other than TMR_0 to TMR3, WDT_0,

and WDT_1 and system clock oscillator are also stopped. The contents of the CPU’s internal

registers, the data in internal RAM, and the statuses of the internal peripheral modules (excluding

the SCI and the A/D converter) and I/O ports are retained.

24.8.2

Exiting Subsleep Mode

• Subsleep mode is exited by an interrupt (interrupts from internal peripheral modules, NMI pin,

IRQ7 to IRQ0), or signals at the RES or STBY pin.

• Exiting Subsleep Mode by Interrupts

When an interrupt occurs, subsleep mode is exited and interrupt exception processing starts.

In the case of

IRQ7 to IRQ0 interrupts, subsleep mode is not cancelled if the corresponding

enable bit/pin function switching bit has been cleared to 0, and, in the case of interrupts from

the internal peripheral modules, the interrupt enable register has been set to disable the

reception of that interrupt, or is masked by the CPU.

• Exiting Subsleep Mode by RES Pin or MRES Pin

For exiting subsleep mode by the

RES or MRES pin, see section 24.4.2, Clearing Software

Standby Mode.

• Exiting Subsleep Mode by STBY Pin

When the

STBY pin or MRES pin level is driven low, a transition is made to hardware standby

mode.

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