H8SSLASH2224 datasheet(960/1071 Pages) RENESAS

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Section 27 Electrical Characteristics

Rev. 5.00 Aug 08, 2006 page 874 of 982

REJ09B0054-0500

(1) Clock Timing

Table 27.17 lists the clock timing.

Table 27.17 Clock Timing

Condition A (F-ZTAT version and masked ROM version):

VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V,

Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 32.768 kHz,

2 to 16.0 MHz, Ta = –20°C to +75°C (regular

specifications)

Condition B (Masked ROM version): VCC = 2.2 V to 3.6 V, AVCC = 2.2 V to 3.6 V,

Vref = 2.2 V to AVCC, VSS = AVSS = 0 V, φ = 32.768 kHz,

2 to 6.25 MHz, Ta = –20°C to +75°C (regular

specifications), Ta = –40°C to +85°C (wide-range

specifications)

Condition C (F-ZTAT version and masked ROM version):

VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V,

Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 32.768 kHz,

10.0 to 20.0 MHz, Ta = –20°C to +75°C (regular

specifications), Ta = –40°C to +85°C (wide-range

specifications)

Condition A

Condition B

Condition C

Test

Item

Symbol Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

Conditions

Clock cycle

time

tcyc

62.5



500

160



500



100

Clock high

pulse width

tCH



Clock low

pulse width

tCL



Clock rise

time

tCr



Clock fall time tCf



Figure

27.10

Oscillation

stabilization

time at reset

(crystal)

tOSC1



Figure

27.11

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