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H8S/2224 Scheda tecnica(PDF) 1028 Page - Renesas Technology Corp |
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H8S/2224 Scheda tecnica(HTML) 1028 Page - Renesas Technology Corp |
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1028 / 1071 page ![]() Section 27 Electrical Characteristics Rev. 5.00 Aug 08, 2006 page 942 of 982 REJ09B0054-0500 (4) Timing of On-Chip Peripheral Modules Table 27.56 lists the timing of on-chip peripheral modules. Table 27.56 Timing of On-Chip Peripheral Modules Condition A (ZTAT version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V,φ = 32.768 kHz, 2 to 10 MHz,Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B (F-ZTAT version, masked ROM version): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 32.768 kHz, 2 to 13.5MHz,Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition C (Masked ROM version): VCC = 2.2 V to 3.6 V, AVCC = 2.2 V to 3.6 V, Vref = 2.2 V to AVCC, VSS = AVSS = 0 V, φ = 32.768 kHz, 2 to 6.25 MHz,Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition A Condition B Condition C Item Symbol Min Max Min Max Min Max Unit Test Conditions I/O port Output data delay time tPWD 100 100 150 ns Figure 27.24 Input data setup time tPRS 50 50 80 Input data hold time tPRH 50 50 80 TPU Timer output delay time tTOCD 100 100 150 ns Figure 27.25 Timer input setup time tTICS 50 40 60 Timer clock input setup time tTCKS 50 40 60 ns Figure 27.26 Timer clock Single edge tTCKWH 1.5 1.5 1.5 tcyc pulse width Both edges tTCKWL 2.5 2.5 2.5 |
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