H8SSLASH2224 datasheet(144/1071 Pages) RENESAS

144 / 1071 page

Section 1 Overview

Rev. 5.00 Aug 08, 2006 page 58 of 982

REJ09B0054-0500

Pin No.

Type

Symbol

TFP-100B

TFP-100BV

TFP-100G

TFP-100GV

FP-100B*

FP-100BV*

FP-100A*

FP-100AV*

2 I/O

Function

System

control

BREQ

Input

Used by an external bus master to request the

bus mastership to this LSI.

BACK

Output Indicates that the bus mastership has been

granted to an external bus master.

FEW

Input

Enables/disables programming the flash

memory.

Interrupts

NMI*

Input

Nonmaskable interrupt pin. If this pin is not used,

it should be fixed-high.

IRQ7

IRQ6

IRQ5

IRQ4

IRQ3

IRQ2

IRQ1

IRQ0

Input

These pins request a maskable interrupt.

Address bus

A23 to A0

37 to 15,

40 to 18, 16 Output Outputs Address.

Data bus

D15 to D0 100 to 96,

11 to 1

100, 99,

14 to 1

Input/

output

Used as the bidirectional data bus.

Bus control

CS7

CS6

CS5

CS4

CS3

CS2

CS1

CS0

Output Select signals for areas 7 to 0.

Output When this pin is low, it indicates valid address

output on the address bus.

Output When this pin is low, it indicates that the external

address space is being read.

HWR

Output Strobe signal: Writes to the external address bus

to indicate valid data on the upper data bus (D15

to D8).

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