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H8S/2224 Scheda tecnica(PDF) 279 Page - Renesas Technology Corp |
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H8S/2224 Scheda tecnica(HTML) 279 Page - Renesas Technology Corp |
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279 / 1071 page ![]() Section 7 Bus Controller Rev. 5.00 Aug 08, 2006 page 193 of 982 REJ09B0054-0500 T1 Address bus φ CS0 AS Data bus T2 T3 T1 T2 T1 Full access T2 RD Burst access Only lower address changed Read data Read data Read data Figure 7.19 Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1) T1 CS0 AS T2 T1 T1 RD Address bus φ Data bus Full access Burst access Only lower address changed Read data Read data Read data Figure 7.20 Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0) |
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