ATtiny261-ESSZ datasheet(129/227 Pages) ATMEL

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7753C–AVR–07/09

ATtiny261/ATtiny461/ATtiny861

The 4-bit counter can be both read and written via the data bus, and can generate an overflow

interrupt. Both the USI Data Register and the counter are clocked simultaneously by the same

clock source. This allows the counter to count the number of bits received or transmitted and

generate an interrupt when the transfer is complete. Note that when an external clock source is

selected the counter counts both clock edges. In this case the counter counts the number of

edges, and not the number of bits. The clock can be selected from three different sources: The

USCK pin, Timer/Counter0 Compare Match or from software.

The Two-wire clock control unit can generate an interrupt when a start condition is detected on

the Two-wire bus. It can also generate wait states by holding the clock pin low after a start con-

dition is detected, or after the counter overflows.

17.3

Functional Descriptions

17.3.1

Three-wire Mode

The USI Three-wire mode is compliant to the Serial Peripheral Interface (SPI) mode 0 and 1, but

does not have the slave select (SS) pin functionality. However, this feature can be implemented

in software if necessary. Pin names used by this mode are: DI, DO, and USCK.

Figure 17-2. Three-wire Mode Operation, Simplified Diagram

Figure 17-2 shows two USI units operating in Three-wire mode, one as Master and one as

Slave. The two USI Data Register are interconnected in such way that after eight USCK clocks,

the data in each register are interchanged. The same clock also increments the USI’s 4-bit coun-

ter. The Counter Overflow (interrupt) Flag, or USIOIF, can therefore be used to determine when

a transfer is completed. The clock is generated by the Master device software by toggling the

USCK pin via the PORT Register or by writing a one to the USITC bit in USICR.

SLAVE

MASTER

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

USCK

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

USCK

PORTxn

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