ATtiny261-ESSZ datasheet(126/227 Pages) ATMEL

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7753C–AVR–07/09

ATtiny261/ATtiny461/ATtiny861

• Bit 2 - TOIE1: Timer/Counter1 Overflow Interrupt Enable

When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $004) is

executed if an overflow in Timer/Counter1 occurs. The Overflow Flag (Timer1) is set (one) in the

Timer/Counter Interrupt Flag Register - TIFR.

16.11.13 TIFR – Timer/Counter1 Interrupt Flag Register

• Bit 7- OCF1D: Output Compare Flag 1D

The OCF1D bit is set (one) when compare match occurs between Timer/Counter1 and the data

value in OCR1D - Output Compare Register 1D. OCF1D is cleared by hardware when executing

the corresponding interrupt handling vector. Alternatively, OCF1D is cleared, after synchroniza-

tion clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1D, and OCF1D

are set (one), the Timer/Counter1 D compare match interrupt is executed.

• Bit 6 - OCF1A: Output Compare Flag 1A

The OCF1A bit is set (one) when compare match occurs between Timer/Counter1 and the data

value in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing

the corresponding interrupt handling vector. Alternatively, OCF1A is cleared, after synchroniza-

tion clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1A, and OCF1A

are set (one), the Timer/Counter1 A compare match interrupt is executed.

• Bit 5 - OCF1B: Output Compare Flag 1B

The OCF1B bit is set (one) when compare match occurs between Timer/Counter1 and the data

value in OCR1B - Output Compare Register 1A. OCF1B is cleared by hardware when executing

the corresponding interrupt handling vector. Alternatively, OCF1B is cleared, after synchroniza-

tion clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1B, and OCF1B

are set (one), the Timer/Counter1 B compare match interrupt is executed.

• Bit 2 - TOV1: Timer/Counter1 Overflow Flag

In Normal Mode and Fast PWM Mode the TOV1 bit is set (one) each time the counter reaches

TOP at the same clock cycle when the counter is reset to BOTTOM. In Phase and Frequency

Correct PWM Mode the TOV1 bit is set (one) each time the counter reaches BOTTOM at the

same clock cycle when zero is clocked to the counter.

The bit TOV1 is cleared by hardware when executing the corresponding interrupt handling vec-

tor. Alternatively, TOV1 is cleared, after synchronization clock cycle, by writing a logical one to

the flag. When the SREG I-bit, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and

TOV1 are set (one), the Timer/Counter1 Overflow interrupt is executed.

Bit

76543210

0x38 (0x58)

OCF1D

OCF1A

OCF1B

OCF0A

OCF0B

TOV1

TOV0

ICF0

TIFR

Read/Write

R/W

Initial value

00000000

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