CDPCLK4 datasheet(168/274 Pages) ALTERA

168 / 274 page

9–10

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family

Configuration Features

Cyclone III Device Handbook

August 2012

Altera Corporation

Volume 1

Initialization

In Cyclone III device family, the clock source for initialization is either a 10-MHz

(typical) internal oscillator (separate from the AS internal oscillator) or an optional

CLKUSR

pin. By default, the internal oscillator is the clock source for initialization. If

you use the internal oscillator, the device provides itself with enough clock cycles for a

proper initialization. When using the internal oscillator, you do not need to send

additional clock cycles from an external source to the CLKUSR pin during the

initialization stage. Additionally, you can use the CLKUSR pin as a user I/O pin.

You also have the flexibility to synchronize initialization of multiple devices or to

delay initialization with the CLKUSR option. The CLKUSR pin allows you to control

when your device enters user mode for an indefinite amount of time. You can turn on

the Enable user-supplied start-up clock (CLKUSR) option in the Quartus II software

from the General tab of the Device and Pin Options dialog box. When you turn on

the Enable user supplied start-up clock option (CLKUSR) option, the CLKUSR pin is

the initialization clock source. Supplying a clock on the CLKUSR pin does not affect the

configuration process. After the configuration data is accepted and CONF_DONE goes

high, the Cyclone III device family requires a certain amount of clock cycles to

initialize and to enter user mode.

Table 9–5 lists the required clock cycles for proper initialization in Cyclone III device

family.

Table 9–6 lists the maximum CLKUSR frequency (fMAX) for Cyclone III device family.

1 If you use the optional CLKUSR pin and the nCONFIG pin is pulled low to restart

configuration during device initialization, ensure that the CLKUSR pin continues to

toggle when nSTATUS is low (a maximum of 230 s).

User Mode

An optional INIT_DONE pin is available that signals the end of initialization and the

start of user mode with a low-to-high transition. The Enable INIT_DONE Output

option is available in the Quartus II software from the General tab of the Device and

Pin Options

dialog box. If you use the INIT_DONE pin, it is high due to an external

10-k pull-up resistor when nCONFIG is low and during the beginning of

configuration. After the option bit to enable INIT_DONE is programmed into the device

Table 9–5. Initialization Clock Cycles Required in Cyclone III Device Family

Device

Initialization Clock Cycles

Cyclone III

3,185

Cyclone III LS

3,192

Table 9–6. Maximum CLKUSR Frequency for Cyclone III Device Family

Device

fMAX (MHz)

Cyclone III

133

Cyclone III LS

100

CDPCLK4 Scheda tecnica(PDF) 168 Page - Altera Corporation

CDPCLK4 Scheda tecnica(HTML) 168 Page - Altera Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL