CDPCLK4 datasheet(258/274 Pages) ALTERA

258 / 274 page

11–6

Chapter 11: SEU Mitigation in the Cyclone III Device Family

Error Detection Timing

Cyclone III Device Handbook

December 2011

Altera Corporation

Volume 1

Table 11–5 lists the minimum and maximum error detection frequencies.

You can set a lower clock frequency by specifying a division factor in the Quartus II

software (for more information, refer to “Software Support” on page 11–7). The

divisor is a power of two (2), where n is between 0 and 8. The divisor ranges from one

through 256. Refer to Equation 11–1.

CRC calculation time depends on the device and the error detection clock frequency.

Table 11–6 lists the estimated time for each CRC calculation with minimum and

maximum clock frequencies for Cyclone III device family.

Table 11–5. Minimum and Maximum Error Detection Frequencies

Device Type

Error

Detection

Frequency

Maximum Error

Detection

Frequency

Minimum Error

Detection

Frequency

Valid Divisors (2)

Cyclone III

device family

80 MHz/2n

80 MHz

312.5 kHz

0, 1, 2, 3, 4, 5, 6, 7, 8

Equation 11–1. Error Detection Frequency

Table 11–6. CRC Calculation Time

Device

Minimum Time (ms) (1)

Maximum Time (s)

(2)

Cyclone III

EP3C5

2.29

EP3C10

2.29

EP3C16

3.17

EP3C25

4.51

EP3C40

7.48

EP3C55

11.77

EP3C80

15.81

EP3C120

22.67

Cyclone III LS

EP3CLS70

21.24

EP3CLS100

21.24

EP3CLS150

40.27

EP3CLS200

40.27

Notes to Table 11–6:

(1) The minimum time corresponds to the maximum error detection clock frequency and may vary with different

processes, voltages, and temperatures (PVT).

(2) The maximum time corresponds to the minimum error detection clock frequency and may vary with different PVT.

Error detection frequency

80 MHz

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