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FS23 Scheda tecnica(PDF) 156 Page - NXP Semiconductors |
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FS23 Scheda tecnica(HTML) 156 Page - NXP Semiconductors |
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156 / 230 page ![]() NXP Semiconductors FS23 Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers 22.36 M_LDT_CFG1 Bit 15 14 13 12 11 10 9 8 Write LDT_AFTER_RUN Read LDT_AFTER_RUN Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Write LDT_AFTER_RUN Read LDT_AFTER_RUN Reset 0 0 0 0 0 0 0 0 Table 145. M_LDT_CFG1 register bit allocation Bit Symbol Description Configure and read the after run LDT LDT value in Normal mode 0 to 15 LDT_AFTER_RUN POR, LDT count started Table 146. M_LDT_CFG1 register bit description 22.37 M_LDT_CFG2 Bit 15 14 13 12 11 10 9 8 Write LDT_WUP_L Read LDT_WUP_L Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Write LDT_WUP_L Read LDT_WUP_L Reset 0 0 0 0 0 0 0 0 Table 147. M_LDT_CFG2 register bit allocation Bit Symbol Description Configure and read the 16 less significant bits of wake-up LDT LDT value in LP mode (LSB) 0 to 15 LDT_WUP_L POR, LDT count started Table 148. M_LDT_CFG2 register bit description FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback 156 / 230 |
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