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FS23 Scheda tecnica(PDF) 174 Page - NXP Semiconductors |
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FS23 Scheda tecnica(HTML) 174 Page - NXP Semiconductors |
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174 / 230 page ![]() NXP Semiconductors FS23 Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers Bit Symbol Description OTP fuse load Request an assertion of LIMP2 0 No action 1 LIMP2 assertion 4 LIMP2_REQ POR, self-clear Select LIMP2 polarity or PWM frequency 00 PWM frequency = 100 Hz (Default high) 01 Default high (Active low) 10 PWM frequency = 100 Hz (Default low) 11 Default low (Active high) 5 to 6 LIMP2_CFG OTP fuse load Select LIMP2 PWM duty cycle 00 PWM duty cycle = 20 % 01 PWM duty cycle = 10 % 10 PWM duty cycle = 5 % 11 PWM duty cycle = 2.5 % 7 to 8 LIMP2_DC_CFG POR Table 180. FS_LIMP12_CFG register bit description...continued 22.54 FS_FS0B_LIMP0_REL Bit 15 14 13 12 11 10 9 8 Write RELEASE_FS0B_LIMP0 Read 0 0 0 0 0 0 0 0 Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Write RELEASE_FS0B_LIMP0 Read 0 0 0 0 0 0 0 0 Reset 0 0 0 0 0 0 0 0 Table 181. FS_FS0B_LIMP0_REL register bit allocation Bit Symbol Description Write secured 16 bits word to release FS0B and/or LIMP0 Write 3'b011,~WD_TOKEN[0:12] to release FS0B Write 3'b110,~WD_TOKEN[3:15] to release LIMP0 Write 3'b101,~WD_TOKEN[0:6],~WD_TOKEN[10:15] to release both FS0B and LIMP0 0 to 15 RELEASE_FS0B_LIMP0 Reset on power-on reset (POR) Table 182. FS_FS0B_LIMP0_REL register bit description FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback 174 / 230 |
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