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FS23 Scheda tecnica(PDF) 181 Page - NXP Semiconductors |
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FS23 Scheda tecnica(HTML) 181 Page - NXP Semiconductors |
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181 / 230 page ![]() NXP Semiconductors FS23 Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers 23 OTP register mapping Address Register # Adr_6 Adr_5 Adr_4 Adr_3 Adr_2 Adr_1 Adr_0 Reference OTP_DEVICE_VER 0 0 0 1 1 1 0 0 Section 24.1 OTP_DEVICE_VER1 1 0 0 1 1 1 0 1 Section 24.2 OTP_PROG_ID 2 0 0 1 1 1 1 0 Section 24.3 OTP_V1_CFG1 3 0 0 1 1 1 1 1 Section 24.4 OTP_V1_CFG2 4 0 1 0 0 0 0 0 Section 24.5 OTP_V1_CFG3 5 0 1 0 0 0 0 1 Section 24.6 OTP_V1_CFG4 6 0 1 0 0 0 1 0 Section 24.7 OTP_V1_CFG5 7 0 1 0 0 0 1 1 Section 24.8 Reserved 8 0 1 0 0 1 0 0 - OTP_V1_CFG7 9 0 1 0 0 1 0 1 Section 24.9 OTP_V1_CFG8 10 0 1 0 0 1 1 0 Section 24.10 OTP_V1_CFG9 11 0 1 0 0 1 1 1 Section 24.11 OTP_V2_CFG 12 0 1 0 1 0 0 0 Section 24.12 OTP_V3_CFG 13 0 1 0 1 0 0 1 Section 24.13 OTP_HVIO_CFG1 14 0 1 0 1 0 1 0 Section 24.14 OTP_HVIO_CFG2 15 0 1 0 1 0 1 1 Section 24.15 OTP_LVIO_CFG1 16 0 1 0 1 1 0 0 Section 24.16 OTP_LVIO_CFG2 17 0 1 0 1 1 0 1 Section 24.17 OTP_IO_OUT_SEL_CFG 18 0 1 0 1 1 1 0 Section 24.18 OTP_MAIN_SYS_I2C_CFG 19 0 1 0 1 1 1 1 Section 24.19 OTP_FS_SYS_CFG 20 0 1 1 0 0 0 0 Section 24.20 OTP_OVUV_CFG1 21 0 1 1 0 0 0 1 Section 24.21 OTP_OVUV_CFG2 22 0 1 1 0 0 1 0 Section 24.22 OTP_OVUV_CFG3 23 0 1 1 0 0 1 1 Section 24.23 OTP_OVUV_CFG4 24 0 1 1 0 1 0 0 Section 24.24 OTP_UV_DGLT_CFG 25 0 1 1 0 1 0 1 Section 24.25 OTP_LIMP_OV_DGLT_CFG 26 0 1 1 0 1 1 0 Section 24.26 OTP_RSTB_IMPACT_CFG 27 0 1 1 0 1 1 1 Section 24.27 Table 191. OTP Register mapping FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback 181 / 230 |
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