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FS23 Scheda tecnica(PDF) 182 Page - NXP Semiconductors |
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FS23 Scheda tecnica(HTML) 182 Page - NXP Semiconductors |
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182 / 230 page  NXP Semiconductors FS23 Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers Orange = HVBUCK version only. Green = HVLDO version only Register Address Default bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 OTP_DEVICE_VER 0x1C 0x00 KEY_OFFON_EN_OTP CAN_EN_OTP LIN_EN_OTP LDTIM_EN_OTP HSD13_EN_OTP HSD24_EN_OTP V2_EN_OTP V1_PNP_EN_OTP OTP_DEVICE_VER1 0x1D 0x00 RSTB_DUR_OTP ABIST_EN_OTP FCCU_EN_OTP FS0B_EN_OTP LIMP0_EN_OTP V0MON_EN_OTP Reserved Reserved OTP_PROG_ID 0x1E 0x00 PROG_IDH_OTP[3] PROG_IDH_OTP[2] PROG_IDH_OTP[1] PROG_IDH_OTP[0] PROG_IDL_OTP[3] PROG_IDL_OTP[2] PROG_IDL_OTP[1] PROG_IDL_OTP[0] OTP_V1_CFG1 0X1F 0x00 Reserved BUCK_ SRHSON_OTP[2] BUCK_ SRHSON_OTP[1] BUCK_ SRHSON_OTP[0] BUCK_ SRHSOFF_OTP[1] BUCK_ SRHSOFF_OTP[0] BUCK_SS_OTP[1] BUCK_SS_OTP[0] OTP_V1_CFG2 0x20 0x00 Reserved Reserved BUCK_CLK_OTP BUCK_RCOMP_OTP[2] BUCK_RCOMP_OTP[1] BUCK_RCOMP_OTP[0] BUCK_CCOMP_OTP[1] BUCK_CCOMP_OTP[0] OTP_V1_CFG3 0x21 0x00 Reserved V1_OCLS_EN_OTP BUCK_SC_OTP[5] BUCK_SC_OTP[4] BUCK_SC_OTP[3] BUCK_SC_OTP[2] BUCK_SC_OTP[1] BUCK_SC_OTP[0] OTP_V1_CFG4 0x22 0x00 Reserved BUCK_PK_OC_ PFM_OTP[2] BUCK_PK_OC_ PFM_OTP[1] BUCK_PK_OC_ PFM_OTP[0] BUCK_PFM_ TOFF_OTP[1] BUCK_PFM_ TOFF_OTP[0] BUCK_PFM_ TON_OTP[1] BUCK_PFM_ TON_OTP[0] OTP_V1_CFG5 0x23 0x00 BUCK_LP_ DVS_OTP{1] BUCK_LP_ DVS_OTP{0] BUCK_PK_OC_ PWM_OTP[2] BUCK_PK_OC_ PWM_OTP[1] BUCK_PK_OC_ PWM_OTP[0] BUCK_AVG_OC_ PWM_OTP[2] BUCK_AVG_OC_ PWM_OTP[1] BUCK_AVG_OC_ PWM_OTP[0] OTP_V1_CFG7 0x25 0x00 Reserved VV1_BUCK_OTP[6] VV1_BUCK_OTP[5] VV1_BUCK_OTP[4] VV1_BUCK_OTP[3] VV1_BUCK_OTP[2] VV1_BUCK_OTP[1] VV1_BUCK_OTP[0] OTP_V1_CFG8 0x26 0x00 Reserved VV1_LP_BUCK_OTP[6] VV1_LP_BUCK_OTP[5] VV1_LP_BUCK_OTP[4] VV1_LP_BUCK_OTP[3] VV1_LP_BUCK_OTP[2] VV1_LP_BUCK_OTP[1] VV1_LP_BUCK_OTP[0] OTP_V1_CFG9 0x27 0x00 VBOS2V1_SW_ ALWAYS_EN_OTP V1MON_OTP CONF_OV_V1_OTP CONF_TSD_V1_OTP CONF_OC_V1_OTP VV1_LDO_OTP CONF_OC_ TO_V1_OTP VBOS2V1_SW_ LP_EN_OTP OTP_V2_CFG 0x28 0x00 Reserved V2MON_OTP CONF_OV_V2_OTP CONF_TSD_V2_OTP CONF_OC_V2_OTP VV2_OTP V2_SLOT_OTP[1] V2_SLOT_OTP[0] OTP_V3_CFG 0x29 0x00 Reserved V3MON_OTP CONF_OV_V3_OTP CONF_TSD_V3_OTP CONF_OC_V3_OTP VV3_OTP V3_SLOT_OTP[1] V3_SLOT_OTP[0] OTP_HVIO_CFG1 0X2A 0x00 WK1PUPD_OTP[1] WK1PUPD_OTP[0] WK2PUPD_OTP[1] WK2PUPD_OTP[0] HVIO1_SLOT_OTP[1] HVIO1_SLOT_OTP[0] HVIO2_SLOT_OTP[1] HVIO2_SLOT_OTP[0] OTP_HVIO_CFG2 0X2B 0x00 HVIO1_OUT_EN_OTP HVIO1_OUT_ DFLT_OTP HVIO1PUPD_OTP[1] HVIO1PUPD_OTP[0] HVIO2_OUT_EN_OTP HVIO2_OUT_ DFLT_OTP HVIO2PUPD_OTP[1] HVIO2PUPD_OTP[0] OTP_LVIO_CFG1 0X2C 0x00 LVIO4_OUT_DFT_OTP LVIO3_OUT_DFT_OTP LVIO3PUPD_OTP[1] LVIO3PUPD_OTP[0] LVIO3_LS_EN_OTP LVIO3_HS_EN_OTP LVIO3_SLOT_OTP[1] LVIO3_SLOT_OTP[0] OTP_LVIO_CFG2 0X2D 0x00 LVI5PUPD_OTP[1] LVI5PUPD_OTP[0] LVIO4PUPD_OTP[1] LVIO4PUPD_OTP[0] LVIO4_LS_EN_OTP LVIO4_HS_EN_OTP LVIO4_SLOT_OTP[1] LVIO4_SLOT_OTP[0] OTP_IO_OUT_SEL_CFG 0X2E 0x00 Reserved Reserved HS3_SEL_OTP HS1_SEL_OTP LVO4_SEL_OTP LVO3_SEL_OTP HVO2_SEL_OTP HVO1_SEL_OTP OTP_MAIN_SYS_I2C_CFG 0X2F 0x00 MOD_CONF_OTP MOD_EN_OTP SLOT_BYP_OTP SPI_EN_OTP I2CDEVADDR_OTP[3] I2CDEVADDR_OTP[2] I2CDEVADDR_OTP[1] I2CDEVADDR_OTP[0] OTP_FS_SYS_CFG 0x30 0x00 Reserved Reserved INIT_CRC_DIS_OTP FS_LPOFF_OTP FS_DUR_CFG_OTP WD_INF_OTP RSTB8S_DIS_OTP FIRST_FAULT_ EN_OTP OTP_OVUV_CFG1 0x31 0x00 V1MON_UVTH_OTP[3] V1MON_UVTH_OTP[2] V1MON_UVTH_OTP[1] V1MON_UVTH_OTP[0] V1MON_OVTH_OTP[3] V1MON_OVTH_OTP[2] V1MON_OVTH_OTP[1] V1MON_OVTH_OTP[0] OTP_OVUV_CFG2 0x32 0x00 V2MON_UVTH_OTP[3] V2MON_UVTH_OTP[2] V2MON_UVTH_OTP[1] V2MON_UVTH_OTP[0] V2MON_OVTH_OTP[3] V2MON_OVTH_OTP[2] V2MON_OVTH_OTP[1] V2MON_OVTH_OTP[0] OTP_OVUV_CFG3 0x33 0x00 V3MON_UVTH_OTP[3] V3MON_UVTH_OTP[2] V3MON_UVTH_OTP[1] V3MON_UVTH_OTP[0] V3MON_OVTH_OTP[3] V3MON_OVTH_OTP[2] V3MON_OVTH_OTP[1] V3MON_OVTH_OTP[0] OTP_OVUV_CFG4 0x34 0x00 V0MON_UVTH_OTP[3] V0MON_UVTH_OTP[2] V0MON_UVTH_OTP[1] V0MON_UVTH_OTP[0] V0MON_OVTH_OTP[3] V0MON_OVTH_OTP[2] V0MON_OVTH_OTP[1] V0MON_OVTH_OTP[0] OTP_UV_DGLT_CFG 0x35 0x00 V0MON_ UVDGLT_OTP[1] V0MON_ UVDGLT_OTP[0] V1MON_ UVDGLT_OTP[1] V1MON_ UVDGLT_OTP[0] V2MON_ UVDGLT_OTP[1] V2MON_ UVDGLT_OTP[0] V3MON_ UVDGLT_OTP[1] V3MON_ UVDGLT_OTP[0] OTP_LIMP_OV_DGLT_CFG 0x36 0x00 LIMP2_CFG_OTP[1] LIMP2_CFG_OTP[0] LIMP1_CFG_OTP[1] LIMP1_CFG_OTP[0] V0MON_OVDGLT_OTP V1MON_OVDGLT_OTP V2MON_OVDGLT_OTP V3MON_OVDGLT_OTP OTP_RSTB_IMPACT_CFG 0x37 0x00 V0UV_RSTB_ IMPACT_OTP V0OV_RSTB_ IMPACT_OTP V1UV_RSTB_ IMPACT_OTP V1OV_RSTB_ IMPACT_OTP V2UV_RSTB_ IMPACT_OTP V2OV_RSTB_ IMPACT_OTP V3UV_RSTB_ IMPACT_OTP V3OV_RSTB_ IMPACT_OTP Table 192. OTP register map content FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback 182 / 230 |
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