FS23 datasheet(207/230 Pages) NXP

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NXP Semiconductors

FS23

Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers

24.26 OTP_LIMP_OV_DGLT_CFG

Bit

Write

Read

LIMP2_CFG_OTP

LIMP1_CFG_OTP

V0MON_

OVDGLT_OTP

V1MON_

OVDGLT_OTP

V2MON_

OVDGLT_OTP

V3MON_

OVDGLT_OTP

Reset

Table 243. OTP_LIMP_OV_DGLT_CFG register bit allocation

Bit

Symbol

Description

Select V3MON OV deglitcher time

0 V3MON OV deglitcher = 25 µs

1 V3MON OV deglitcher = 45 µs

V3MON_OVDGLT_OTP

Reset on power-on reset

Select V2MON OV deglitcher time

0 V2MON OV deglitcher = 25 µs

1 V2MON OV deglitcher = 45 µs

V2MON_OVDGLT_OTP

Reset on power-on reset

Select V1MON OV deglitcher time

0 V1MON OV deglitcher = 25 µs

1 V1MON OV deglitcher = 45 µs

V1MON_OVDGLT_OTP

RESET ON POWER ON RESET

Select V0MON OV deglitcher time (VMON_EXT)

0 V0MON OV deglitcher = 25 µs

1 V0MON OV deglitcher = 45 µs

V0MON_OVDGLT_OTP

Reset on power-on reset

Select LIMP1 polarity or PWM frequency

00 PWM frequency = 1.25 Hz with 50 % duty cycle (default high)

01 Default high (Active low)

10 PWM frequency = 1.25 Hz with 50 % duty cycle (default low)

11 Default low (Active high)

4 to 5

LIMP1_CFG_OTP

Reset on power-on reset

Select LIMP2 polarity or PWM frequency

00 PWM frequency = 100 Hz (default high)

01 Default high (Active low)

10 PWM frequency = 100 Hz (default low)

11 Default low (Active high)

6 to 7

LIMP2_CFG_OTP

Reset on power-on reset

Table 244. OTP_LIMP_OV_DGLT_CFG register bit description

FS23

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Product data sheet

Rev. 7.0 — 16 October 2024

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