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FS23 Scheda tecnica(PDF) 218 Page - NXP Semiconductors |
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FS23 Scheda tecnica(HTML) 218 Page - NXP Semiconductors |
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218 / 230 page  NXP Semiconductors FS23 Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers 27 Appendix: ISO 11898-2016 parameter cross-reference list ISO 11898-2:2016 NXP data sheet Parameter Notation Symbol Parameter HS-PMA dominant output characteristics Single-ended voltage on CAN_H VCAN_H VCANH_OUT_DOM CAN dominant output voltage on pin CANH, Active mode Single-ended voltage on CAN_L VCAN_L VCANL_OUT_DOM CAN dominant output voltage on pin CANL, Active mode Differential voltage on normal bus load VDiff Differential voltage on effective resistance during arbitration VDiff Optional: Differential voltage on extended bus load range VDiff VCAN_OUT_DIFF_DOM CAN bus differential output voltage, Active mode, dominant state HS-PMA driver symmetry Driver symmetry Vsym VCAN_OUT_SYM CAN output voltage symmetry, Active mode Maximum HS-PMA driver output current Absolute current on CAN_H ICAN_H ICANH_OUT_SC CANH short circuit output current Absolute current on CAN_L ICAN_L ICANL_OUT_SC CANL short circuit output current HS-PMA recessive output characteristics, bus biasing active/inactive Single-ended output voltage on CAN_H VCAN_H Single-ended output voltage on CAN_L VCAN_L VCAN_OUT_REC_WC CAN recessive output voltage, Wake-capable mode, no load Differential output voltage VDiff VCAN_OUT_DIFF_REC CAN bus differential output voltage, Wake-capable mode, Recessive state, no load Optional HS-PMA transmit dominant time-out Transmit dominant time-out tdom TCAN_DOM_TO CAN CANTXD dominant timeout time HS-PMA static receiver input characteristics, bus biasing active/inactive VCAN_IN_DIFF CAN differential receiver threshold voltage, Active or Listen-only mode VCAN_IN_DIFF_LP CAN differential low-power receiver threshold voltage, Wake-capable mode VCAN_IN_DIFF_REC CAN Recessive state differential input voltage range Recessive state differential input voltage range Dominant state differential input voltage range VDiff VDiff VCAN_IN_DIFF_DOM CAN dominant state differential input voltage range HS-PMA receiver input resistance (matching) Differential internal resistance RDiff RCAN_IN_DIFF CAN differential input resistance Single-ended internal resistance RCAN_H, RCAN_L RCAN_IN_CM CAN Common mode input resistance Matching of internal resistance mR ΔRCAN_IN CAN input resistance deviation HS-PMA implementation loop delay requirement Loop delay tLoop TCAN_LOOP CAN loop delay time from CANTXD to CANRXD Optional HS-PMA implementation data signal timing requirements for use with bit rates above 1 Mbit/s up to 2 Mbit/s Transmitted recessive bit width @ 2 Mbit/s tBit(Bus) TCAN_BIT_BUS_2M CAN transmitted recessive bit width @ 2 Mbps Table 247. ISO 11898-2:2016 to NXP data sheet parameter conversion FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback 218 / 230 |
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