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FS23 Scheda tecnica(PDF) 225 Page - NXP Semiconductors

Il numero della parte FS23
Spiegazioni elettronici  Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers
PDF  230 Pages
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Produttore elettronici  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
Logo NXP - NXP Semiconductors

FS23 Scheda tecnica(HTML) 225 Page - NXP Semiconductors

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NXP Semiconductors
FS23
Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers
Tab. 107. M_IOWU_CFG register bit allocation ............ 133
Tab. 108. M_IOWU_CFG register bit description .......... 133
Tab. 109. M_IOWU_EN register bit allocation ...............134
Tab. 110. M_IOWU_EN register bit description .............135
Tab. 111. M_IOWU_FLG register bit allocation .............136
Tab. 112. M_IOWU_FLG register bit description ...........136
Tab. 113. M_WU1_EN register bit allocation ................ 137
Tab. 114. M_WU1_EN register bit description .............. 138
Tab. 115. M_WU1_FLG register bit allocation ...............138
Tab. 116. M_WU1_FLG register bit description ............ 138
Tab. 117. M_TIMER1_CFG register bit allocation .........139
Tab. 118. M_TIMER1_CFG register bit description .......140
Tab. 119. M_TIMER2_CFG register bit allocation .........141
Tab. 120. M_TIMER2_CFG register bit description .......141
Tab. 121. M_TIMER3_CFG register bit allocation .........142
Tab. 122. M_TIMER3_CFG register bit description .......142
Tab. 123. M_PWM1_CFG register bit allocation ........... 144
Tab. 124. M_PWM1_CFG register bit description ......... 144
Tab. 125. M_PWM2_CFG register bit allocation ........... 144
Tab. 126. M_PWM2_CFG register bit description ......... 144
Tab. 127. M_PWM3_CFG register bit allocation ........... 145
Tab. 128. M_PWM3_CFG register bit description ......... 145
Tab. 129. M_TIMER_PWM_CTRL register bit
allocation ....................................................... 146
Tab. 130. M_TIMER_PWM_CTRL register bit
description ..................................................... 146
Tab. 131. M_CS_CFG register bit allocation .................147
Tab. 132. M_CS_CFG register bit description ...............147
Tab. 133. M_CS_FLG_MSK register bit allocation ........148
Tab. 134. M_CS_FLG_MSK register bit description ......148
Tab. 135. M_HSx_SRC_CFG register bit allocation ......149
Tab. 136. M_HSx_SRC_CFG register bit description ....149
Tab. 137. M_HSx_CTRL register bit allocation ............. 151
Tab. 138. M_HSx_CTRL register bit description ........... 151
Tab. 139. M_HSx_FLG register bit allocation ................152
Tab. 140. M_HSx_FLG register bit description ..............152
Tab. 141. M_HSx_MSK register bit allocation ...............153
Tab. 142. M_HSx_MSK register bit description .............154
Tab. 143. M_AMUX_CTRL register bit allocation ..........155
Tab. 144. M_AMUX_CTRL register bit description ........155
Tab. 145. M_LDT_CFG1 register bit allocation ............. 156
Tab. 146. M_LDT_CFG1 register bit description ........... 156
Tab. 147. M_LDT_CFG2 register bit allocation ............. 156
Tab. 148. M_LDT_CFG2 register bit description ........... 156
Tab. 149. M_LDT_CFG3 register bit allocation ............. 157
Tab. 150. M_LDT_CFG3 register bit description ........... 157
Tab. 151. M_LDT_CTRL register bit allocation ............. 157
Tab. 152. M_LDT_CTRL register bit description ........... 157
Tab. 153. M_CAN register bit allocation ........................158
Tab. 154. M_CAN register bit description ......................158
Tab. 155. M_LIN register bit allocation ..........................159
Tab. 156. M_LIN register bit description ....................... 159
Tab. 157. M_CAN_LIN_MSK register bit allocation .......160
Tab. 158. M_CAN_LIN_MSK register bit description .....161
Tab. 159. M_MEMORY0 register bit allocation ............. 162
Tab. 160. M_MEMORY0 register bit description ........... 162
Tab. 161. M_MEMORY1 register bit allocation ............. 162
Tab. 162. M_MEMORY1 register bit description ........... 162
Tab. 163. FS_I_OVUV_CFG1 register bit allocation ..... 163
Tab. 164. FS_I_OVUV_CFG1 register bit description ... 163
Tab. 165. FS_I_OVUV_CFG2 register bit allocation ..... 164
Tab. 166. FS_I_OVUV_CFG2 register bit description ... 164
Tab. 167. FS_I_FCCU_CFG register bit allocation ........166
Tab. 168. FS_I_FCCU_CFG register bit description ..... 166
Tab. 169. FS_I_FSSM_CFG register bit allocation ........167
Tab. 170. FS_I_FSSM_CFG register bit description ..... 168
Tab. 171. FS_I_WD_CFG register bit allocation ........... 169
Tab. 172. FS_I_WD_CFG register bit description ......... 169
Tab. 173. FS_WDW_CFG register bit allocation ........... 171
Tab. 174. FS_WDW_CFG register bit description .........171
Tab. 175. FS_WD_TOKEN register bit allocation ..........172
Tab. 176. FS_WD_TOKEN register bit description ........172
Tab. 177. FS_WD_ANSWER register bit allocation ...... 173
Tab. 178. FS_WD_ANSWER register bit description .... 173
Tab. 179. FS_LIMP12_CFG register bit allocation ........ 173
Tab. 180. FS_LIMP12_CFG register bit description ......173
Tab. 181. FS_FS0B_LIMP0_REL register bit
allocation ....................................................... 174
Tab. 182. FS_FS0B_LIMP0_REL register bit
description ..................................................... 174
Tab. 183. FS_ABIST register bit allocation ................... 175
Tab. 184. FS_ABIST register bit description ................. 175
Tab. 185. FS_SAFETY_OUTPUTS register bit
allocation ....................................................... 176
Tab. 186. FS_SAFETY_OUTPUTS register bit
description ..................................................... 177
Tab. 187. FS_SAFETY_FLG register bit allocation ....... 178
Tab. 188. FS_SAFETY_FLG register bit description ..... 178
Tab. 189. FS_CRC register bit allocation ......................180
Tab. 190. FS_CRC register bit description ....................180
Tab. 191. OTP Register mapping ..................................181
Tab. 192. OTP register map content .............................182
Tab. 193. OTP_DEVICE_VER register bit allocation .....183
Tab. 194. OTP_DEVICE_VER register bit description .. 183
Tab. 195. OTP_DEVICE_VER1 register bit allocation ...184
Tab. 196. OTP_DEVICE_VER1 register bit
description ..................................................... 184
Tab. 197. OTP_PROG_ID register bit allocation ........... 185
Tab. 198. OTP_PROG_ID register bit description .........185
Tab. 199. OTP_V1_CFG1 register bit allocation ........... 186
Tab. 200. OTP_V1_CFG1 register bit description ......... 186
Tab. 201. OTP_V1_CFG2 register bit allocation ........... 187
Tab. 202. OTP_V1_CFG2 register bit description ......... 187
Tab. 203. OTP_V1_CFG3 register bit allocation ........... 188
Tab. 204. OTP_V1_CFG3 register bit description ......... 188
Tab. 205. OTP_V1_CFG4 register bit allocation ........... 188
Tab. 206. OTP_V1_CFG4 register bit description ......... 188
Tab. 207. OTP_V1_CFG5 register bit allocation ........... 190
Tab. 208. OTP_V1_CFG5 register bit description ......... 190
Tab. 209. OTP_V1_CFG7 register bit allocation ........... 190
Tab. 210. OTP_V1_CFG7 register bit description ......... 191
Tab. 211. OTP_V1_CFG8 register bit allocation ........... 191
Tab. 212. OTP_V1_CFG8 register bit description ......... 191
Tab. 213. OTP_V1_CFG9 register bit allocation ........... 192
Tab. 214. OTP_V1_CFG9 register bit description ......... 192
Tab. 215. OTP_V2_CFG register bit allocation ............. 193
Tab. 216. OTP_V2_CFG register bit description ........... 193
Tab. 217. OTP_V3_CFG register bit allocation ............. 194
FS23
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© 2024 NXP B.V. All rights reserved.
Product data sheet
Rev. 7.0 — 16 October 2024
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