FS23 datasheet(227/230 Pages) NXP

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NXP Semiconductors

FS23

Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers

Figures

Fig. 1.

Functional block diagram .................................. 2

Fig. 2.

Typical application diagram ...............................4

Fig. 3.

Full FS23 part numbers breakdown .................. 5

Fig. 4.

Simplified FS23 part numbers breakdown .........5

Fig. 5.

Part numbers mapping versus base feature

sets ....................................................................5

Fig. 6.

FS2320 Block diagram (HVBUCK) ....................9

Fig. 7.

FS2300 Block diagram (HVLDO1) .................. 10

Fig. 8.

FS2320 Pin configuration (HVBUCK) ..............11

Fig. 9.

FS2300 Pin configuration (HVLDO1) .............. 11

Fig. 10.

Simplified state machine ................................. 20

Fig. 11.

Detailed functional state diagram ....................24

Fig. 12.

Simplified INIT state diagram .......................... 25

Fig. 13.

Power sequencing ...........................................26

Fig. 14.

Power-up sequence example ..........................27

Fig. 15.

Debug mode ....................................................28

Fig. 16.

OTP mode time chart ......................................28

Fig. 17.

Debug pin (DBG) circuitry ............................... 28

Fig. 18.

Simplified VBOS state diagram .......................31

Fig. 19.

Triangular spread spectrum ............................ 35

Fig. 20.

Pseudo-random triangular spread spectrum ... 36

Fig. 21.

HVBUCK schematic with connection to V1_

IN .....................................................................36

Fig. 22.

HVBUCK efficiency in force PWM mode ......... 40

Fig. 23.

HVBUCK efficiency in PFM mode ...................41

Fig. 24.

HVLDO1 application schematic, with

optional external PNP ..................................... 42

Fig. 25.

HVLDO2 application schematic .......................44

Fig. 26.

HVLDO3 application schematic. ......................46

Fig. 27.

AMUX block diagram. ..................................... 48

Fig. 28.

Key OFF – Key ON feature description. ..........50

Fig. 29.

Example of HVIO pins configuration in the

slots, at power up ........................................... 52

Fig. 30.

Example of LVIO pins configuration in the

slots, at power-up. ...........................................53

Fig. 31.

Cyclic sense example with HS1 and HVIO1 ....58

Fig. 32.

Cyclic sense schematic example with HS1

and HVIO1 ...................................................... 58

Fig. 33.

Long duration timer block diagram ..................61

Fig. 34.

Long duration timer functions ..........................63

Fig. 35.

CAN FD transceiver internal diagram, with

external components .......................................65

Fig. 36.

CAN transceiver state machine .......................66

Fig. 37.

CAN Wake-up timing diagram .........................67

Fig. 38.

CAN timing definition according to ISO

11898-2:2016 ...................................................68

Fig. 39.

LIN transceiver internal diagram ..................... 71

Fig. 40.

LIN transceiver state machine .........................72

Fig. 41.

LIN wake-up timing diagram ........................... 73

Fig. 42.

Timing diagram of LIN duty cycle ....................74

Fig. 43.

Fail-safe features block diagram ..................... 77

Fig. 44.

Window watchdog time diagram ..................... 79

Fig. 45.

Watchdog error counter configurations ............80

Fig. 46.

Watchdog refresh counter configurations ........ 81

Fig. 47.

Fault recovery strategy principle ..................... 82

Fig. 48.

FCCU bi-stable protocol ..................................83

Fig. 49.

Fault Error Counter diagram with maximum

value = 2 or 6 ................................................. 89

Fig. 50.

Fault Error Counter diagram with maximum

value = 8 or 12 ............................................... 90

Fig. 51.

RSTB pin implementation ............................... 93

Fig. 52.

FS0B pin implementation ................................ 94

Fig. 53.

LIMP0 pin implementation ...............................95

Fig. 54.

CRC encoder example ..................................104

Fig. 55.

SPI timing diagram ........................................106

Fig. 56.

Example of application schematic with 450

kHz HVBUCK version, SPI interface ............. 209

Fig. 57.

Example of application schematic with 2.25

MHz HVBUCK version, SPI interface ............210

Fig. 58.

Example of application schematic,

HVLDO1 version with internal PMOS only,

I2C interface ..................................................211

Fig. 59.

Example of application schematic,

HVLDO1 version with external PNP, SPI

interface .........................................................212

FS23

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Product data sheet

Rev. 7.0 — 16 October 2024

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