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NXP Semiconductors

FS23

Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers

20.2.3 Cyclic redundant check

An 8-bit CRC is required for each write and read SPI command. Computation of a CRC is derived from the

mathematics of polynomial division, modulo two. The CRC polynomial used is x^8+x^4+x^3+x^2+1 (identified

by 0x1D) with a SEED value of hexadecimal '0xFF'.

Figure 54 is an example of CRC encoding HW implementation:

aaa-046864

1*1

0*X

1*X2

1*X3

1*X4

0*X5

0*X6

0*X7

1*X8

Input

Data

Figure 54. CRC encoder example

20.2.3.1 CRC encoding procedure

The effect of the CRC encoding procedure is shown in Table 70. The seed value is appended into the most

significant bits of the shift register.

Seed

Read/write

Data_MSB

Data_LSB

0xFF

Bits[31:25]

Bit[24]

Bits[23:16]

Bits[15:8]

Seed…

… padded with the message to encode

… padded with 8

zeros

Table 70. Data preparation for CRC encoding

1. Using a serial CRC calculation method, the transmitter rotates the seed and data into the least significant

bits of the shift register.

2. During the serial CRC calculation, the seed and the data bits are XOR compared with the polynomial data

bits. When the MSB is logic 1, the comparison result is loaded in the register, otherwise the data bits are

simply shifted. It must be noted the 32-bit message to be processed must have the bits corresponding to the

CRC byte all equal to zero (00000000).

3. Once the CRC is calculated, it replaces the CRC byte initially set to all zeros and is transmitted.

20.2.3.2 CRC decoding procedure

1. The seed value is loaded into the most significant bits of the receive register.

2. Using a serial CRC calculation method, the receiver rotates the received message and CRC into the least

significant bits of the shift register in the order received (MSB first).

3. When the calculation on the last bit of the CRC is rotated into the shift register, the shift register contains the

CRC check result.

• If the shift register contains all zeros, the CRC is correct.

• If the shift register contains a value other than zero, the CRC is incorrect.

FS23

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Product data sheet

Rev. 7.0 — 16 October 2024

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