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Rev. 0A | October 2022

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IS43/46LR32320C

IS43/46LR16640C

The 1Gb Mobile DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 1,073,741,824-bits. It is internally

configured as a quad-bank DRAM. The 1Gb Mobile DDR SDRAM uses a double data rate architecture to achieve high speed operation. The

double data rate architecture is essentially a 2n-prefetch architecture, with an interface designed to transfer two data words per clock cycle

at the I/O balls, single read or write access for the 2Gb Mobile DDR SDRAM consists of a single 2n-bit wide, one-clock-cycle data transfer at

the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O balls.

Read and Write accesses to the Mobile DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed

number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a

READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be

accessed (BA0, BA1 select the bank; A0–A12(A13) select the row). The address bits registered coincident with the READ or WRITE command

are used to select the starting column location for the burst access.

It should be noted that the DLL signal that is typically used on standard DDR devices is not necessary on the Mobile DDR SDRAM. It has

been omitted to save power.

Prior to normal operation, the Mobile DDR SDRAM must be powered up and initialized. The following sections provide detailed information

covering device initialization, register definition, command descriptions and device operation.

Power up and Initialization

Mobile DDR SDRAM must be powered up and initialized in a predefined manner. Power must be applied to VDD and VDDQ (simultaneously).

After power up, an initial pause of 200 usec is required. And a precharge all command will be issued to the Mobile DDR. Then, 2 or more

Auto refresh cycles will be provided. After the Auto refresh cycles are completed, a Mode Register Set(MRS) command will be issued to

program the specific mode of operation (Cas Latency, Burst length, etc.) And a Extended Mode Register Set(EMRS) command will be issued

to Partial Array Self Refresh(PASR). The following these cycles, the Mobile DDR SDRAM is ready for normal operation. To ensure device

functionality, there is a predefined sequence that must occur at device power up or if there is any interruption of device power.

To properly initialize the Mobile DDR SDRAM, this sequence must be followed:

1. To prevent device latch-up, it is recommended the core power (VDD) and I/O power (VDDQ) be from the same power source and brought

up simultaneously. If separate power sources are used, VDD must lead VDDQ.

2. Once power supply voltages are stable and the CKE has been driven HIGH, it is safe to apply the clock.

3. Once the clock is stable, a 200μs (minimum) delay is required by the Mobile DDR SDRAM prior to applying an executable command.

During this time, NOP or DESELECT commands must be issued on the command bus.

4. Issue a PRECHARGE ALL command.

5. Issue NOP or DESELECT commands for at least tRP time.

6. Issue an AUTO REFRESH command followed by NOP or DESELECT commands for at least tRFC time. Issue a second AUTO REFRESH

command followed by NOP or DESELECT commands for at least tRFC time. As part of the individualization sequence, two AUTO REFRESH

commands must be issued. Typically, both of these commands are issued at this stage as described above.

7. Using the LOAD MODE REGISTER command, load the standard mode register as desired.

8. Issue NOP or DESELECT commands for at least tMRD time.

9. Using the LOAD MODE REGISTER command, load the extended mode register to the desired operating modes. Note that the order in

which the standard and extended mode registers are programmed is not critical.

10. Issue NOP or DESELECT commands for at least tMRD time.

11. The Mobile DDR SDRAM has been properly initialized and is ready to receive any valid command.

Functional Description