16

Rev. 0A | October 2022

www.issi.com - dram@issi.com

IS43/46LR32320C

IS43/46LR16640C

S3

S2

S1

S0

Manufacturer ID

1

0

1

1

ISSI

All

others

Other

manufacturers

Data Bus (DQ)

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ7

Figure8 : Status Register Read (SRR)

31~8

7

6

5

4

3

2

1

0

Reserved

Revision ID

Manufacturer

Mode Register (Sx)

DQ6

DQ31~DQ8

Status Register Read

The Status Register Read (SRR) command allows the user to access the manufacturer device information. It is optional for the user. This

product supports 8 bits of encoded data in the Status Register, and can be output onto DQ0~DQ7, with a fixed burst length (BL) of 2.

The Manufacturer's ID is on S0~S3 and the Device Revision ID is on S4~S7. The register bit range S8~S31 is reserved.

The SRR command sequence is as follows:

• All banks must be idle, and Reads and Writes completed

• A Mode Register Set (MRS) command is issued with BA0=1, BA1=0, and A0~A12=0 (x32) or A0~A13 (x16) to initiate SRR

• After a time period tSRR, a Read command is issued to any bank or address

• The next valid command may be issued a time period tSRC after the Read command

The Read command causes the Status Register data to be output after two or three clock cycles, whichever corresponds to the CAS Latency

setting. In the first half of the Read burst, the DQ8~DQ31 values are “Don’t Care,” and in the second half of the Read burst, the

DQ0~DQ31 values are "Don't Care”.